diff --git a/k1-spl-dram.md b/k1-spl-dram.md index 5566dae..5ddaf57 100644 --- a/k1-spl-dram.md +++ b/k1-spl-dram.md @@ -284,4 +284,319 @@ handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x303 length 0xff Now press Ctrl + C to drop into the U-Boot shell. Enjoy! :-) --- -[source link](https://gist.github.com/orangecms/8624aa82bab4931f787b5eee572f7668) \ No newline at end of file +[source link](https://gist.github.com/orangecms/8624aa82bab4931f787b5eee572f7668) +--- + +oreboot DRAM init + +NOTE: I reverse engineered the DRAM training blob and translated the other DRAM init code from U-Boot, staged at https://github.com/orangecms/oreboot/tree/all-the-things-wip/src/mainboard/spacemit/k1x/bt0 + +NOTE: In order to get the binary with the necessary header, I hacked a bit into the vendor tool, created a custom JSON config for it (see below), and fixed some bits in U-Boot. See https://github.com/orangecms/spacemit-u-boot/tree/v2022.10-k1 - it's a bit messy. I could flash the eMMC with that U-Boot, but then got authentication (header verfiication) errors when booting. No clue why. So just use the tool to create the binary; ./tools/build_binary_file.py -c oreboot.json -o oreboot.bin. + +Will see if we can port the tool to create the header to make it easier to use. +```JSON +{ + "_comment": { + "info": "bootinfo build configuration script", + "key word": { + "image": "image definition", + "module": "image module definition", + "data": "image item data config" + } + }, + "info": { + "arch": "RISCV64", + "description": "spacemit k1x fsbl image" + }, + "image": [ + { + "module": "ROTPK", + "data": [ + { + "pubkey": { + "name": "rsakeypair0", + "algorithm": "RSA2048", + "source": "board/spacemit/k1-x/configs/key/rsakeypair0_prv.key", + "align": 256 + } + } + ] + }, + { + "module": "image_header", + "data": [ + { + "structure": [ + "name, header0, 0", + "magic, AIHD, 4", + "version, 1, 1", + "secure, 0, 1", + "reserved, 0, 2", + "imgsize, 0x0200, 8", + "load_addr, 0x100, 8", + "pad, 0xA5, 8" + ] + } + ] + }, + { + "module": "image_config", + "data": [ + { + "structure": [ + "name, keydata, 0", + "key_default, 0, 4", + "table_num, 2, 4", + { + "structure": [ + "name, keytable0, 0", + "key_name, spl, 16", + "key_id, 0, 4" + ] + }, + "pad, 0, 452" + ] + } + ] + }, + { + "module": "oem_pubkey", + "data": [ + { + "structure": [ + "name, oem_key, 0", + { + "pubkey": { + "name": "spl_pubkey", + "algorithm": "RSA2048", + "source": "board/spacemit/k1-x/configs/key/spl_pubkey_prv.key", + "align": 256 + } + }, + "reserved, 0, 1792" + ] + } + ] + }, + { + "module": "cert0", + "data": [ + { + "signature": { + "name": "signature0", + "algorithm": "SHA256+RSA2048", + "key": "rsakeypair0", + "source": "header0 + keydata + oem_key", + "align": 256 + } + } + ] + }, + { + "module": "padding", + "data": [ + { + "structure": [ + "pad, 0, 992" + ] + } + ] + }, + { + "module": "spl", + "data": [ + { + "structure": [ + "name, header1, 0", + "magic, AIHD, 4", + "version, 1, 1", + "secure, 0, 1", + "reserved, 0, 2", + "imgsize, sizeof(fsbl), 8", + "load_addr, 0x512, 8", + "pad, 0xA5, 8" + ] + }, + { + "file": { + "name": "fsbl", + "source": "spacemit-k1x-bt0.bin", + "align": 32 + } + }, + { + "signature": { + "name": "signature1", + "algorithm": "SHA256+RSA2048", + "key": "spl_pubkey", + "source": "header1 + fsbl", + "align": 256 + } + } + ] + } + ] +} +``` +Here is a log. + +NOTE: The panic is intentional. +``` +oreboot 🦀 bt0 +RISC-V arch 8000000058000001 +RISC-V core vendor: SpacemiT (0x0710) +RISC-V implementation: X60 (0x1000000049772200) +RISC-V hart ID 0 +HeaderInfo { + magic: 0x6ded1e0, + crc32: 0xc23e034a, + chipid: 0x9bb6cc1b8baeb641, + mac_addr: 0xaeba42965924c6c9, + version: 0x3691b684, + cs_num: 0xb56abde1, +} +dump 1024 bytes @c0800040 +a4f0e0ba5793715641938afc43a1adc23d3e945629b111c817037cec782476ec +d4a3be098fb5cb75d4191c2d6b87fe2e10593975ba5739c37345d04d47b98ff2 +14cdbdc2fff228183c0c9a9b2099766740719c70cd018b7b30503e01fdd6dd40 +db66d04e65f9f9a9e1f08edead41df8d84556dc989ec7f4e82b9198cf5eec9ef +7913086b2bfff2855a6525fac8cfed30a89b6a69c951276fc2c7a412118fac42 +8c7bd55f0dbed9230717a3538a920ee32fa189a6ea79956a702e391916745007 +414948440100000000020000000000000001000000000000a5a5a5a5a5a5a5a5 +000000000200000073706c000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +d263462f1b7be1bbc2a160f5ece41575781d7120b3c95101927eca04e9d5c47e +c8639b0d530a14ceada30910d9add7b04739c7d7dcba696ae1efff835e53ec40 +fd50f916c7d2d6c9c004388fb574e38eef23ae58eb591fad0aff47a4c82720b5 +eb0649b58b5a664db8a088ad6a9a3f88951618380e9b2a9368f9449a0c3b9227 +3cb179c42baaa309375797cd2894a341b557b7fcdef90ede70a7b5b7abac917f +1dec10dfe100426ebc1571062c154934856acc84f38f6dae0d66a436e25be1db +f819a9193c07a8a594a4d667a16d8397a4203705502929fadd603f9f63f864da +8d2dedf8fee3cb4c330137fcca99e6cbf8e6eebced7fe3dcf42e5fd99dbaab3d +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +ADDR[0xc0000304]=0x00800400 +PHY INIT done +wait DRAM INIT +DRAM INIT done +DRAM Mode register Init done. +DDR size (density): 4096MB +MR 8: 18 +DEBUG-ADDR[0xc0000200]:0x000f0001 +DEBUG-ADDR[0xc0000204]:0x00000000 +DEBUG-ADDR[0xc0000208]:0x800f0001 +DEBUG-ADDR[0xc000020c]:0x00000000 +DEBUG-ADDR[0xc0000220]:0x05030632 +DEBUG-ADDR[0xc0000224]:0x05030632 +self refresh start +self refresh done +Training start... +Training init... +Dump margin and setting before training... +write leveling +read gate train +read gate training pass +read gate training pass +0xc0040070 = 0x00012121 +0xc0040170 = 0x00012222 +0xc0041070 = 0x00011f1f +0xc0041170 = 0x00012020 +read training +each RX Vref corresponding min margin + 00: 22, 01: 22, 02: 22, 03: 23, + 04: 23, 05: 24, 06: 24, 07: 24, + 08: 24, 09: 23, 10: 23, 11: 22, + 12: 21, 13: 18, 14: 17, 15: 16, +optimize RX Vref adjust = 5, corresponding best margin = 24 +Optimize fine RX vref step: 5 +write training +each TX Vref corresponding min margin + 00: 20, 01: 20, 02: 20, 03: 20, + 04: 20, 05: 20, 06: 20, 07: 20, + 08: 20, 09: 20, 10: 20, 11: 20, + 12: 20, 13: 20, 14: 20, 15: 20, +optimize TX Vref adjust = 21, corresponding best margin = 29 +Optimize fine TX vref step: 21 +Training status [0xc0058000]=0x00000000 +change to 1600 +frequency change done! +self refresh start +self refresh done +Training start... +Training init... +Dump margin and setting before training... +write leveling +read gate train +read gate training pass +read gate training pass +0xc0044070 = 0x00012222 +0xc0044170 = 0x00012222 +0xc0045070 = 0x00012020 +0xc0045170 = 0x00012020 +read training +each RX Vref corresponding min margin + 00: 14, 01: 15, 02: 15, 03: 16, + 04: 16, 05: 17, 06: 17, 07: 17, + 08: 17, 09: 16, 10: 16, 11: 15, + 12: 14, 13: 11, 14: 10, 15: 9, +optimize RX Vref adjust = 5, corresponding best margin = 17 +Optimize fine RX vref step: 5 +write training +each TX Vref corresponding min margin + 00: 12, 01: 12, 02: 12, 03: 12, + 04: 12, 05: 12, 06: 12, 07: 12, + 08: 12, 09: 12, 10: 12, 11: 12, + 12: 12, 13: 12, 14: 12, 15: 12, +optimize TX Vref adjust = 21, corresponding best margin = 30 +Optimize fine TX vref step: 21 +Training status [0xc0058000]=0x00000000 +change to 2400 +frequency change done! +self refresh start +self refresh done +Training start... +Training init... +Dump margin and setting before training... +write leveling +read gate train +read gate training pass +read gate training pass +0xc0048070 = 0x00012323 +0xc0048170 = 0x00012323 +0xc0049070 = 0x00012121 +0xc0049170 = 0x00012121 +read training +each RX Vref corresponding min margin + 00: 8, 01: 8, 02: 9, 03: 9, + 04: 10, 05: 10, 06: 11, 07: 10, + 08: 10, 09: 10, 10: 9, 11: 8, + 12: 8, 13: 4, 14: 0, 15: 0, +optimize RX Vref adjust = 6, corresponding best margin = 11 +Optimize fine RX vref step: 6 +write training +each TX Vref corresponding min margin + 00: 10, 01: 10, 02: 10, 03: 10, + 04: 10, 05: 10, 06: 10, 07: 10, + 08: 10, 09: 10, 10: 10, 11: 10, + 12: 10, 13: 10, 14: 10, 15: 10, +optimize TX Vref adjust = 21, corresponding best margin = 31 +Optimize fine TX vref step: 21 +Training status [0xc0058000]=0x00000000 +change to 2400 +frequency change done! +[bt0] panic in 'src/mainboard/spacemit/k1x/bt0/src/dram.rs' line 1589 +[bt0] TODO +```