From 81a1f6eb636797276dd56d6bdcd27904d4327fef Mon Sep 17 00:00:00 2001 From: blizzardfinnegan Date: Wed, 12 Feb 2025 13:34:33 -0500 Subject: [PATCH] Musebook Oreboot DRAM Init Posted on Pastebin at https://pastebin.com/C9y3Kh2b Signed-off-by: Blizzard Finnegan --- MuseVook DRAM Init Code | 193 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 MuseVook DRAM Init Code diff --git a/MuseVook DRAM Init Code b/MuseVook DRAM Init Code new file mode 100644 index 0000000..a2d4f97 --- /dev/null +++ b/MuseVook DRAM Init Code @@ -0,0 +1,193 @@ +sys: 0x1200 +bm:2 +ROM: usb download handler +usb2d_initialize : enter +Controller Run +usb rst int +SETUP: 0x80 0x6 0x100 +usb rst int +SETUP: 0x0 0x5 0x31 +SETUP: 0x80 0x6 0x100 +SETUP: 0x80 0x6 0x200 +SETUP: 0x80 0x6 0x200 +SETUP: 0x80 0x6 0x300 +SETUP: 0x80 0x6 0x302 +SETUP: 0x80 0x6 0x301 +SETUP: 0x80 0x6 0x30a +SETUP: 0x0 0x9 0x1 +usb_rx_bytes : len= 4096 pBuf= 0xc0838720 +SETUP: 0x80 0x6 0x302 +SETUP: 0x80 0x6 0x304 +fastboot_handle_command: max-download-size +usb_tx_bytes : len= 65 pBuf= 0xc083fe88 +usb_rx_bytes : len= 4096 pBuf= 0xc0838720 +fastboot_handle_command: 00008cc0 +Starting download of 36032 bytes +usb_tx_bytes : len= 65 pBuf= 0xc083fe88 +usb_rx_bytes : len= 36032 pBuf= 0xc0800000 +usb_tx_bytes : len= 65 pBuf= 0xc083fe88 +usb_rx_bytes : len= 4096 pBuf= 0xc0838720 +fastboot_handle_command: continue +usb_tx_bytes : len= 65 pBuf= 0xc083fe88 +j... +oreboot ð bt0 +RISC-V arch 8000000058000001 +RISC-V core vendor: SpacemiT (0x0710) +RISC-V implementation: X60 (0x1000000049772200) +RISC-V hart ID 0 +Boot mode: 0xc08381a0 +Boot entry: 0xffe03b36 +HeaderInfo { + magic: 0x6ded1e0, + crc32: 0xc23e034a, + chipid: 0x9bb6cc1b8baeb641, + mac_addr: 0xaeba42965924c6c9, + version: 0x3691b684, + cs_num: 0xb56abde1, +} +dump 1024 bytes @c0800000 +e0d1de064a033ec241b6ae8b1bccb69bc9c624599642baae84b69136e1bd6ab5 +14333f67d54c698202db5bed4fce294aef31f0c44d6db9e490c3577f606d3821 +a4f0e0ba5793715641938afc43a1adc23d3e945629b111c817037cec782476ec +d4a3be098fb5cb75d4191c2d6b87fe2e10593975ba5739c37345d04d47b98ff2 +14cdbdc2fff228183c0c9a9b2099766740719c70cd018b7b30503e01fdd6dd40 +db66d04e65f9f9a9e1f08edead41df8d84556dc989ec7f4e82b9198cf5eec9ef +7913086b2bfff2855a6525fac8cfed30a89b6a69c951276fc2c7a412118fac42 +8c7bd55f0dbed9230717a3538a920ee32fa189a6ea79956a702e391916745007 +414948440100000000020000000000000001000000000000a5a5a5a5a5a5a5a5 +000000000200000073706c000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +d263462f1b7be1bbc2a160f5ece41575781d7120b3c95101927eca04e9d5c47e +c8639b0d530a14ceada30910d9add7b04739c7d7dcba696ae1efff835e53ec40 +fd50f916c7d2d6c9c004388fb574e38eef23ae58eb591fad0aff47a4c82720b5 +eb0649b58b5a664db8a088ad6a9a3f88951618380e9b2a9368f9449a0c3b9227 +3cb179c42baaa309375797cd2894a341b557b7fcdef90ede70a7b5b7abac917f +1dec10dfe100426ebc1571062c154934856acc84f38f6dae0d66a436e25be1db +f819a9193c07a8a594a4d667a16d8397a4203705502929fadd603f9f63f864da +8d2dedf8fee3cb4c330137fcca99e6cbf8e6eebced7fe3dcf42e5fd99dbaab3d +ADDR[0xc0000304]=0x00800400 +PHY INIT done +wait DRAM INIT +DRAM INIT done +DRAM Mode register Init done. +DDR size (density): 16384MB +MR 8: 88 +DEBUG-ADDR[0xc0000200]:0x00110001 +DEBUG-ADDR[0xc0000204]:0x00000000 +DEBUG-ADDR[0xc0000208]:0x00110001 +DEBUG-ADDR[0xc000020c]:0x00000002 +DEBUG-ADDR[0xc0000220]:0x05030832 +DEBUG-ADDR[0xc0000224]:0x05030832 +self refresh start +self refresh done +Training start... +Training init... +Dump margin and setting before training... +write leveling +read gate train +read gate training pass +read gate training pass +0xc0040070 = 0x00017474 +0xc0040170 = 0x00017575 +0xc0041070 = 0x00017070 +0xc0041170 = 0x00016f6f +read training +each RX Vref corresponding min margin + 00: 22, 01: 23, 02: 23, 03: 24, + 04: 24, 05: 24, 06: 24, 07: 24, + 08: 23, 09: 23, 10: 22, 11: 22, + 12: 21, 13: 18, 14: 16, 15: 15, +optimize RX Vref adjust = 3, corresponding best margin = 24 +Optimize fine RX vref step: 3 +write training +each TX Vref corresponding min margin + 00: 24, 01: 24, 02: 24, 03: 24, + 04: 24, 05: 24, 06: 24, 07: 24, + 08: 24, 09: 24, 10: 24, 11: 24, + 12: 24, 13: 24, 14: 24, 15: 24, +optimize TX Vref adjust = 21, corresponding best margin = 33 +Optimize fine TX vref step: 21 +Training status [0xc0058000]=0x00000000 +change to 1600 +frequency change done! +self refresh start +self refresh done +Training start... +Training init... +Dump margin and setting before training... +write leveling +read gate train +read gate training pass +read gate training pass +0xc0044070 = 0x00016060 +0xc0044170 = 0x00016161 +0xc0045070 = 0x00015c5c +0xc0045170 = 0x00015b5b +read training +each RX Vref corresponding min margin + 00: 15, 01: 16, 02: 16, 03: 17, + 04: 18, 05: 18, 06: 18, 07: 17, + 08: 16, 09: 16, 10: 15, 11: 15, + 12: 14, 13: 10, 14: 09, 15: 07, +optimize RX Vref adjust = 4, corresponding best margin = 18 +Optimize fine RX vref step: 4 +write training +each TX Vref corresponding min margin + 00: 17, 01: 17, 02: 17, 03: 17, + 04: 17, 05: 17, 06: 17, 07: 17, + 08: 17, 09: 17, 10: 17, 11: 17, + 12: 17, 13: 17, 14: 17, 15: 17, +optimize TX Vref adjust = 21, corresponding best margin = 33 +Optimize fine TX vref step: 21 +Training status [0xc0058000]=0x00000000 +change to 2400 +frequency change done! +self refresh start +self refresh done +Training start... +Training init... +Dump margin and setting before training... +write leveling +read gate train +read gate training pass +read gate training pass +0xc0048070 = 0x00014e4e +0xc0048170 = 0x00014d4d +0xc0049070 = 0x00014a4a +0xc0049170 = 0x00014949 +read training +each RX Vref corresponding min margin + 00: 08, 01: 09, 02: 09, 03: 09, + 04: 09, 05: 10, 06: 09, 07: 09, + 08: 09, 09: 08, 10: 07, 11: 06, + 12: 06, 13: 00, 14: 00, 15: 00, +optimize RX Vref adjust = 5, corresponding best margin = 10 +Optimize fine RX vref step: 5 +write training +each TX Vref corresponding min margin + 00: 10, 01: 10, 02: 10, 03: 10, + 04: 10, 05: 10, 06: 10, 07: 10, + 08: 10, 09: 10, 10: 10, 11: 10, + 12: 10, 13: 10, 14: 10, 15: 10, +optimize TX Vref adjust = 21, corresponding best margin = 35 +Optimize fine TX vref step: 21 +Training status [0xc0058000]=0x00000000 +change to 2400 +frequency change done! +DRAM test: write patterns... +DRAM test: reading back... +DRAM test: done :) +„ \ No newline at end of file