| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u0|rst_controller_001|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_001|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_001|rst_controller_001 |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_001 |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|rst_controller |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| u0|irq_mapper |
5 |
29 |
2 |
29 |
32 |
29 |
29 |
29 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_008 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001 |
217 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb|adder |
36 |
18 |
0 |
18 |
18 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb |
13 |
0 |
4 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux |
966 |
0 |
0 |
0 |
116 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_008 |
110 |
1 |
2 |
1 |
108 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_007 |
110 |
1 |
2 |
1 |
108 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_006 |
110 |
1 |
2 |
1 |
108 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_005 |
110 |
1 |
2 |
1 |
108 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_004 |
110 |
1 |
2 |
1 |
108 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_003 |
111 |
4 |
2 |
4 |
215 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_002 |
111 |
4 |
2 |
4 |
215 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_001 |
110 |
1 |
2 |
1 |
108 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux |
110 |
1 |
2 |
1 |
108 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_008 |
110 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_007 |
110 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_006 |
110 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_005 |
110 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_004 |
110 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_003 |
217 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002 |
217 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001 |
110 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux |
110 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux_001 |
111 |
4 |
2 |
4 |
215 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux |
118 |
81 |
2 |
81 |
964 |
81 |
81 |
81 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_010|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_010 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_009|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_009 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_008|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_008 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_007|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_007 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_006|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_006 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_005|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_005 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002 |
101 |
0 |
2 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001 |
101 |
0 |
6 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router |
101 |
0 |
6 |
0 |
108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|timer_0_s1_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|timer_0_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|timer_0_s1_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|hex0_s1_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|hex0_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|hex0_s1_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|leds_s1_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|leds_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|leds_s1_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|buttons_s1_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|buttons_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|buttons_s1_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|switches_s1_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|switches_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|switches_s1_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_qsys_0_control_slave_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_qsys_0_control_slave_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_qsys_0_control_slave_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo |
141 |
39 |
0 |
39 |
100 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent |
284 |
39 |
46 |
39 |
295 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_instruction_master_agent |
170 |
39 |
76 |
39 |
133 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_data_master_agent |
170 |
39 |
76 |
39 |
133 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|timer_0_s1_translator |
84 |
22 |
33 |
22 |
55 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|hex0_s1_translator |
100 |
6 |
18 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|leds_s1_translator |
100 |
6 |
18 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|buttons_s1_translator |
100 |
6 |
18 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|switches_s1_translator |
100 |
6 |
18 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory2_0_s1_translator |
100 |
7 |
4 |
7 |
86 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_translator |
100 |
5 |
8 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_qsys_0_control_slave_translator |
100 |
6 |
16 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_translator |
100 |
5 |
19 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_instruction_master_translator |
101 |
51 |
0 |
51 |
93 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_0_data_master_translator |
101 |
12 |
0 |
12 |
93 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0 |
351 |
0 |
0 |
0 |
334 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|timer_0 |
23 |
0 |
15 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|sysid_qsys_0 |
3 |
14 |
2 |
14 |
32 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| u0|switches |
12 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0|the_altsyncram|auto_generated |
52 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0 |
56 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_debug_slave_wrapper|the_nios_system_nios2_gen2_0_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_debug_slave_wrapper|the_nios_system_nios2_gen2_0_cpu_debug_slave_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_ocimem|nios_system_nios2_gen2_0_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_ocimem|nios_system_nios2_gen2_0_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_avalon_reg |
48 |
0 |
28 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_im |
54 |
38 |
51 |
38 |
47 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_fifo|the_nios_system_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_fifo|the_nios_system_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_fifo|the_nios_system_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_fifo |
115 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_dtrace|nios_system_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_dtrace |
102 |
0 |
91 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_itrace |
24 |
53 |
24 |
53 |
53 |
53 |
53 |
53 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_dbrk |
87 |
0 |
0 |
0 |
91 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_xbrk |
53 |
5 |
50 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci|the_nios_system_nios2_gen2_0_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_nios2_oci |
154 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|nios_system_nios2_gen2_0_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|nios_system_nios2_gen2_0_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|nios_system_nios2_gen2_0_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|nios_system_nios2_gen2_0_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu|the_nios_system_nios2_gen2_0_cpu_test_bench |
285 |
3 |
251 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0|cpu |
149 |
1 |
29 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2_0 |
149 |
1 |
0 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|leds |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0|the_nios_system_jtag_uart_0_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart_0 |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u0|hex0 |
38 |
25 |
25 |
25 |
39 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
| u0|buttons |
42 |
0 |
28 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0 |
14 |
0 |
0 |
0 |
15 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |