From 8f09867bda53d1ce26b3e92f776cc980f104715b Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Fri, 7 Apr 2017 13:09:31 +0200 Subject: [PATCH] Cleaning --- .../Plugin/DecoderSimplePlugin.scala | 24 ------------------- .../SpinalRiscv/Plugin/IBusCachedPlugin.scala | 7 ------ .../scala/SpinalRiscv/Plugin/SrcPlugin.scala | 6 ++--- 3 files changed, 2 insertions(+), 35 deletions(-) diff --git a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala b/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala index 8c1904ee..08af71cc 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala @@ -117,30 +117,6 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR // logic implementation val decodedBits = Bits(stageables.foldLeft(0)(_ + _.dataType.getBitsWidth) bits) -// val defaultBits = cloneOf(decodedBits) - -// assert(defaultValue == 0) -// defaultBits := defaultValue -// -// val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits)) -// decodedBits := logicOr.foldLeft(defaultBits)(_ | _) - - -// for(i <- decodedBits.range) -// if(defaultCare.testBit(i)) -// defaultBits(i) := Bool(defaultValue.testBit(i)) -// else -// defaultBits(i).assignDontCare() - - -// val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits)) -// val logicAnd = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(~mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits)) -// decodedBits := (defaultBits | logicOr.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)) & ~logicAnd.foldLeft(B(0, decodedBits.getWidth bits))(_ | _) -// if(catchIllegalInstruction){ -// insert(LEGAL_INSTRUCTION) := (for((key, mapping) <- spec) yield ((input(INSTRUCTION) & key.care) === (key.value & key.care))).reduce(_ || _) -// } - - decodedBits := Symplify(input(INSTRUCTION),spec, decodedBits.getWidth) if(catchIllegalInstruction) insert(LEGAL_INSTRUCTION) := Symplify.logicOf(input(INSTRUCTION), SymplifyBit.getPrimeImplicants(spec.unzip._1.toSeq, 32)) diff --git a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala index 6af0d994..aef97a4c 100644 --- a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala +++ b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala @@ -279,22 +279,15 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ val waysHitValid = False val waysHitError = Bool.assignDontCare() val waysHitWord = Bits(wordWidth bit) -// waysHitWord.assignDontCare() val waysRead = for(way <- ways) yield new Area{ val readAddress = Mux(io.cpu.fetch.isStuck,io.cpu.fetch.address,io.cpu.prefetch.address) //TODO FMAX -// val readAddress = io.cpu.prefetch.address val tag = if(asyncTagMemory) way.tags.readAsync(io.cpu.fetch.address(lineRange)) else way.tags.readSync(readAddress(lineRange)) val data = way.datas.readSync(readAddress(lineRange.high downto wordRange.low)) - // val readAddress = request.address - // val tag = way.tags.readAsync(readAddress(lineRange)) - // val data = way.datas.readAsync(readAddress(lineRange.high downto wordRange.low)) - // way.tags.add(new AttributeString("ramstyle","no_rw_check")) - // way.datas.add(new AttributeString("ramstyle","no_rw_check")) waysHitWord := data //Not applicable to multi way when(tag.valid && tag.address === io.cpu.fetch.address(tagRange)) { waysHitValid := True diff --git a/src/main/scala/SpinalRiscv/Plugin/SrcPlugin.scala b/src/main/scala/SpinalRiscv/Plugin/SrcPlugin.scala index 38e9c11f..dbe9ef7e 100644 --- a/src/main/scala/SpinalRiscv/Plugin/SrcPlugin.scala +++ b/src/main/scala/SpinalRiscv/Plugin/SrcPlugin.scala @@ -17,8 +17,6 @@ class SrcPlugin(separatedAddSub : Boolean) extends Plugin[VexRiscv]{ Src1CtrlEnum.RS -> output(REG1), Src1CtrlEnum.FOUR -> B(4), Src1CtrlEnum.IMU -> imm.u.resized - // Src1CtrlEnum.IMZ -> imm.z.resized, - // Src1CtrlEnum.IMJB -> B(0) ) insert(SRC2) := input(SRC2_CTRL).mux( Src2CtrlEnum.RS -> output(REG2), @@ -33,8 +31,8 @@ class SrcPlugin(separatedAddSub : Boolean) extends Plugin[VexRiscv]{ import execute._ // ADD, SUB - val add = (input(SRC1).asUInt + input(SRC2).asUInt).asBits - val sub = (input(SRC1).asUInt - input(SRC2).asUInt).asBits + val add = (input(SRC1).asUInt + input(SRC2).asUInt).asBits.addAttribute("keep") + val sub = (input(SRC1).asUInt - input(SRC2).asUInt).asBits.addAttribute("keep") // SLT, SLTU val less = Mux(input(SRC1).msb === input(SRC2).msb, sub.msb,