From fc835f370e7d9eb09fd04968a63bd5e87e0e0b98 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 4 Jun 2018 19:45:15 +0200 Subject: [PATCH] Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function --- src/main/scala/vexriscv/plugin/Fetcher.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 2606fa0b..6c4a5c24 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -491,7 +491,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val historyWrite = history.writePort val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush) - val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) + val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1)) //Avoid stoping instruction fetch in the middle patch if(compressedGen && cmdToRspStageCount == 1){ @@ -561,6 +561,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, } historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring) + } } }