diff --git a/core/common_components/byte_en_BRAM.sv b/core/common_components/byte_en_bram.sv similarity index 98% rename from core/common_components/byte_en_BRAM.sv rename to core/common_components/byte_en_bram.sv index 94d1bbb..660ae79 100755 --- a/core/common_components/byte_en_BRAM.sv +++ b/core/common_components/byte_en_bram.sv @@ -22,7 +22,7 @@ -module byte_en_BRAM +module byte_en_bram import cva5_config::*; import cva5_types::*; diff --git a/core/fetch_stage/tag_bank.sv b/core/common_components/dual_port_bram.sv old mode 100755 new mode 100644 similarity index 64% rename from core/fetch_stage/tag_bank.sv rename to core/common_components/dual_port_bram.sv index 3afc013..61da14a --- a/core/fetch_stage/tag_bank.sv +++ b/core/common_components/dual_port_bram.sv @@ -1,5 +1,5 @@ /* - * Copyright © 2017-2020 Eric Matthews, Lesley Shannon + * Copyright © 2023 Eric Matthews, Lesley Shannon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,46 +20,51 @@ * Eric Matthews */ -module tag_bank - #( + + +module dual_port_bram + + import cva5_config::*; + import cva5_types::*; + import riscv_types::*; + + #( parameter WIDTH = 32, - parameter LINES = 512 + parameter LINES = 4096 ) ( input logic clk, - input logic rst, - input logic[$clog2(LINES)-1:0] addr_a, - input logic[$clog2(LINES)-1:0] addr_b, input logic en_a, - input logic en_b, input logic wen_a, + input logic[$clog2(LINES)-1:0] addr_a, + input logic[WIDTH-1:0] data_in_a, + output logic[WIDTH-1:0] data_out_a, + + input logic en_b, input logic wen_b, - input logic [WIDTH-1:0] data_in_a, - input logic [WIDTH-1:0] data_in_b, - output logic [WIDTH-1:0] data_out_a, - output logic [WIDTH-1:0] data_out_b + input logic[$clog2(LINES)-1:0] addr_b, + input logic[WIDTH-1:0] data_in_b, + output logic[WIDTH-1:0] data_out_b ); - (* ram_style = "block", ramstyle = "no_rw_check" *) logic [WIDTH-1:0] tag_entry [LINES]; - initial tag_entry = '{default: 0}; + (* ram_style = "block", ramstyle = "no_rw_check" *) logic [WIDTH-1:0] ram [LINES]; + initial ram = '{default: 0}; always_ff @ (posedge clk) begin if (en_a) begin if (wen_a) - tag_entry[addr_a] <= data_in_a; - else - data_out_a <= tag_entry[addr_a]; + ram[addr_a] <= data_in_a; + data_out_a <= ram[addr_a]; end end always_ff @ (posedge clk) begin if (en_b) begin if (wen_b) - tag_entry[addr_b] <= data_in_b; - else - data_out_b <= tag_entry[addr_b]; + ram[addr_b] <= data_in_b; + data_out_b <= ram[addr_b]; end end -endmodule \ No newline at end of file +endmodule diff --git a/core/execution_units/load_store_unit/dcache.sv b/core/execution_units/load_store_unit/dcache.sv index 8674acd..8bb93e3 100644 --- a/core/execution_units/load_store_unit/dcache.sv +++ b/core/execution_units/load_store_unit/dcache.sv @@ -253,7 +253,7 @@ module dcache assign data_read_addr = load_state[LOAD_FILL] ? {addr_utils.getTagLineAddr(stage2_load.addr), word_count} : addr_utils.getDataLineAddr(ls_load.addr); generate for (genvar i=0; i < CONFIG.DCACHE.WAYS; i++) begin : data_bank_gen - byte_en_BRAM #(CONFIG.DCACHE.LINES*CONFIG.DCACHE.LINE_W) data_bank ( + byte_en_bram #(CONFIG.DCACHE.LINES*CONFIG.DCACHE.LINE_W) data_bank ( .clk(clk), .addr_a(data_read_addr), .addr_b(addr_utils.getDataLineAddr(stage2_store.addr)), diff --git a/core/execution_units/load_store_unit/dcache_tag_banks.sv b/core/execution_units/load_store_unit/dcache_tag_banks.sv index 4c5da5c..572db71 100644 --- a/core/execution_units/load_store_unit/dcache_tag_banks.sv +++ b/core/execution_units/load_store_unit/dcache_tag_banks.sv @@ -90,9 +90,8 @@ module dcache_tag_banks //////////////////////////////////////////////////// //Memory instantiation and hit detection generate for (genvar i = 0; i < CONFIG.DCACHE.WAYS; i++) begin : tag_bank_gen - tag_bank #($bits(dtag_entry_t), CONFIG.DCACHE.LINES) dtag_bank ( + dual_port_bram #(.WIDTH($bits(dtag_entry_t)), .LINES(CONFIG.DCACHE.LINES)) dtag_bank ( .clk (clk), - .rst (rst), .en_a (store_req | (miss_req & miss_way[i]) | external_inv), .wen_a ((miss_req & miss_way[i]) | external_inv), .addr_a (porta_addr), diff --git a/core/fetch_stage/branch_predictor.sv b/core/fetch_stage/branch_predictor.sv index 2142211..ef2ea7b 100755 --- a/core/fetch_stage/branch_predictor.sv +++ b/core/fetch_stage/branch_predictor.sv @@ -104,31 +104,37 @@ module branch_predictor genvar i; generate if (CONFIG.INCLUDE_BRANCH_PREDICTOR) for (i=0; i - */ - -module branch_predictor_ram - - import cva5_config::*; - import cva5_types::*; - - #( - parameter C_DATA_WIDTH = 20, - parameter C_DEPTH = 512 - ) - ( - input logic clk, - input logic rst, - input logic [$clog2(C_DEPTH)-1:0] write_addr, - input logic write_en, - input logic [$clog2(C_DEPTH)-1:0] read_addr, - input logic read_en, - input logic [C_DATA_WIDTH-1:0] write_data, - output logic [C_DATA_WIDTH-1:0] read_data - ); - (* ram_style = "block" *)logic [C_DATA_WIDTH-1:0] branch_ram [C_DEPTH-1:0]; - //////////////////////////////////////////////////// - //Implementation - initial branch_ram = '{default: 0}; - always_ff @(posedge clk) begin - if (write_en) - branch_ram[write_addr] <= write_data; - end - always_ff @(posedge clk) begin - if (read_en) - read_data <= branch_ram[read_addr]; - end - //////////////////////////////////////////////////// - //End of Implementation - //////////////////////////////////////////////////// - - //////////////////////////////////////////////////// - //Assertions - - //////////////////////////////////////////////////// - //Trace Interface - -endmodule diff --git a/core/fetch_stage/icache.sv b/core/fetch_stage/icache.sv index 1a7887f..a81463b 100755 --- a/core/fetch_stage/icache.sv +++ b/core/fetch_stage/icache.sv @@ -190,17 +190,17 @@ module icache //Data Banks genvar i; generate for (i=0; i < CONFIG.ICACHE.WAYS; i++) begin : idata_bank_gen - byte_en_BRAM #(CONFIG.ICACHE.LINES*CONFIG.ICACHE.LINE_W) idata_bank ( + dual_port_bram #(.WIDTH(32), .LINES(CONFIG.ICACHE.LINES*CONFIG.ICACHE.LINE_W)) idata_bank ( .clk(clk), - .addr_a(addr_utils.getDataLineAddr(new_request_addr)), - .addr_b(addr_utils.getDataLineAddr({second_cycle_addr[31:SCONFIG.SUB_LINE_ADDR_W+2], word_count, 2'b0})), .en_a(new_request), - .en_b(tag_update_way[i] & l1_response.data_valid), - .be_a('0), - .be_b('1), + .wen_a(0), + .addr_a(addr_utils.getDataLineAddr(new_request_addr)), .data_in_a('0), - .data_in_b(l1_response.data), .data_out_a(data_out[i]), + .en_b(1), + .wen_b(tag_update_way[i] & l1_response.data_valid), + .addr_b(addr_utils.getDataLineAddr({second_cycle_addr[31:SCONFIG.SUB_LINE_ADDR_W+2], word_count, 2'b0})), + .data_in_b(l1_response.data), .data_out_b() ); end endgenerate diff --git a/core/fetch_stage/icache_tag_banks.sv b/core/fetch_stage/icache_tag_banks.sv index 4589566..f350e91 100755 --- a/core/fetch_stage/icache_tag_banks.sv +++ b/core/fetch_stage/icache_tag_banks.sv @@ -63,7 +63,8 @@ module itag_banks genvar i; generate for (i=0; i < CONFIG.ICACHE.WAYS; i++) begin : tag_bank_gen - tag_bank #(SCONFIG.TAG_W+1, CONFIG.ICACHE.LINES) itag_bank (.*, + dual_port_bram #(.WIDTH(SCONFIG.TAG_W+1), .LINES(CONFIG.ICACHE.LINES)) itag_bank (.*, + .clk(clk), .en_a(stage1_adv), .wen_a('0), .addr_a(stage1_line_addr), diff --git a/examples/zedboard/cva5_wrapper.sv b/examples/zedboard/cva5_wrapper.sv index f70292a..654384f 100755 --- a/examples/zedboard/cva5_wrapper.sv +++ b/examples/zedboard/cva5_wrapper.sv @@ -243,7 +243,7 @@ module cva5_wrapper ( endgenerate //arm proc(.*); - byte_en_BRAM #(MEM_LINES, "/home/ematthew/Research/RISCV/software2/riscv-tools/riscv-tests/benchmarks/fft.riscv.hw_init", 1) inst_data_ram ( + byte_en_bram #(MEM_LINES, "/home/ematthew/Research/RISCV/software2/riscv-tools/riscv-tests/benchmarks/fft.riscv.hw_init", 1) inst_data_ram ( .clk(clk), .addr_a(instruction_bram.addr[$clog2(MEM_LINES)- 1:0]), .en_a(instruction_bram.en), diff --git a/local_memory/local_mem.sv b/local_memory/local_mem.sv index 6e1fbfb..5bb7bc6 100644 --- a/local_memory/local_mem.sv +++ b/local_memory/local_mem.sv @@ -36,7 +36,7 @@ module local_mem localparam LINES = (RAM_SIZE/4)*1024; //RAM width is 32-bits, so for RAM_SIZE in KB, divide by 4 and multiply by 1024. - byte_en_BRAM #(LINES, preload_file, USE_PRELOAD_FILE) inst_data_ram ( + byte_en_bram #(LINES, preload_file, USE_PRELOAD_FILE) inst_data_ram ( .clk(clk), .addr_a(portA.addr[$clog2(LINES)- 1:0]), .en_a(portA.en), diff --git a/tools/compile_order b/tools/compile_order index 2699fa1..32fa972 100644 --- a/tools/compile_order +++ b/tools/compile_order @@ -15,6 +15,7 @@ core/types_and_interfaces/external_interfaces.sv core/common_components/lutram_1w_1r.sv core/common_components/lutram_1w_mr.sv +core/common_components/dual_port_bram.sv core/common_components/set_clr_reg_with_rst.sv core/common_components/one_hot_to_integer.sv core/common_components/cycler.sv @@ -26,7 +27,7 @@ core/common_components/toggle_memory_set.sv core/common_components/vendor_support/intel/intel_byte_enable_ram.sv core/common_components/vendor_support/xilinx/xilinx_byte_enable_ram.sv -core/common_components/byte_en_BRAM.sv +core/common_components/byte_en_bram.sv core/execution_units/csr_unit.sv core/execution_units/gc_unit.sv @@ -59,9 +60,7 @@ core/execution_units/div_core.sv core/execution_units/div_unit.sv core/fetch_stage/ras.sv -core/fetch_stage/branch_predictor_ram.sv core/fetch_stage/branch_predictor.sv -core/fetch_stage/tag_bank.sv core/fetch_stage/icache_tag_banks.sv core/fetch_stage/icache.sv core/fetch_stage/fetch.sv