diff --git a/core/register_bank.sv b/core/register_bank.sv
index 3f32024..d4b8542 100644
--- a/core/register_bank.sv
+++ b/core/register_bank.sv
@@ -55,10 +55,10 @@ module register_bank
         if (commit)
             register_file_bank[write_addr] <= new_data;
     end
-    always_comb begin
-        foreach(read_addr[i])
-            data[i] = register_file_bank[read_addr[i]];
-    end
+    
+    generate for (genvar i = 0; i < NUM_READ_PORTS; i++)
+        assign data[i] = register_file_bank[read_addr[i]];
+    endgenerate
 
     ////////////////////////////////////////////////////
     //Assertions