From 207c47abd7b54941e61c2bdbda1c9ee0120b0171 Mon Sep 17 00:00:00 2001 From: Eric Matthews Date: Mon, 16 May 2022 16:48:10 -0400 Subject: [PATCH] Fix AXI support for independent icache/dcache line widths Signed-off-by: Eric Matthews --- core/axi_to_arb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/axi_to_arb.sv b/core/axi_to_arb.sv index 0090f9f..a75ec7a 100755 --- a/core/axi_to_arb.sv +++ b/core/axi_to_arb.sv @@ -166,7 +166,7 @@ module axi_to_arb assign axi_arprot = '0; assign axi_arid = 6'(l2.id); - assign axi_araddr ={l2.addr[29:$clog2(EXAMPLE_CONFIG.DCACHE.LINE_W)], {$clog2(EXAMPLE_CONFIG.DCACHE.LINE_W){1'b0}}, 2'b00}; + assign axi_araddr ={l2.addr, 2'b00} & {25'h1FFFFFF, ~burst_count, 2'b00}; assign write_reference_burst_count = read_modify_write ? 0 : burst_count;