diff --git a/core/common_components/cva5_fifo.sv b/core/common_components/cva5_fifo.sv
index af5d621..0dad17b 100644
--- a/core/common_components/cva5_fifo.sv
+++ b/core/common_components/cva5_fifo.sv
@@ -27,10 +27,6 @@
  */
 module cva5_fifo
 
-    import cva5_config::*;
-    import riscv_types::*;
-    import cva5_types::*;
-    
     #(
         parameter type DATA_TYPE = logic,
         parameter FIFO_DEPTH = 4
diff --git a/core/common_components/lfsr.sv b/core/common_components/lfsr.sv
index 5cfbf48..39bc68d 100644
--- a/core/common_components/lfsr.sv
+++ b/core/common_components/lfsr.sv
@@ -68,7 +68,7 @@ module lfsr
     logic feedback;
     ////////////////////////////////////////////////////
     //Implementation
-    generate if (WIDTH == 2) begin : gen_width_two
+    generate if (WIDTH <= 2) begin : gen_width_one_or_two
         assign feedback = ~value[WIDTH-1];
     end
     else begin : gen_width_three_plus
@@ -84,8 +84,10 @@ module lfsr
     always_ff @ (posedge clk) begin
         if (NEEDS_RESET & rst)
             value <= '0;
-        else if (en)
-            value <= {value[WIDTH-2:0], feedback};
+        else if (en) begin
+            value <= value << 1;
+            value[0] <= feedback;
+        end
     end
 
 endmodule
diff --git a/core/common_components/toggle_memory.sv b/core/common_components/toggle_memory.sv
index bf20db9..ff66bd9 100644
--- a/core/common_components/toggle_memory.sv
+++ b/core/common_components/toggle_memory.sv
@@ -22,16 +22,12 @@
 
 module toggle_memory
 
-    import cva5_config::*;
-    import cva5_types::*;
-    
     # (
         parameter DEPTH = 8,
         parameter NUM_READ_PORTS = 2
     )
     (
         input logic clk,
-        input logic rst,
 
         input logic toggle,
         input logic [$clog2(DEPTH)-1:0] toggle_id,
diff --git a/core/common_components/toggle_memory_set.sv b/core/common_components/toggle_memory_set.sv
index 3029901..2a02eb5 100644
--- a/core/common_components/toggle_memory_set.sv
+++ b/core/common_components/toggle_memory_set.sv
@@ -22,9 +22,6 @@
 
 module toggle_memory_set
 
-    import cva5_config::*;
-    import cva5_types::*;
-    
     # (
         parameter DEPTH = 64,
         parameter NUM_WRITE_PORTS = 3,
@@ -32,7 +29,6 @@ module toggle_memory_set
     )
     (
         input logic clk,
-        input logic rst,
         input logic init_clear,
 
         input logic toggle [NUM_WRITE_PORTS],
@@ -53,7 +49,7 @@ module toggle_memory_set
     //counter for indexing through memories for post-reset clearing/initialization
     lfsr #(.WIDTH($clog2(DEPTH)), .NEEDS_RESET(0))
     lfsr_counter (
-        .clk (clk), .rst (rst),
+        .clk (clk), .rst (1'b0),
         .en(init_clear),
         .value(clear_index)
     );
@@ -76,7 +72,7 @@ module toggle_memory_set
         for (j = 0; j < NUM_WRITE_PORTS+1; j++) begin : write_port_gen
             toggle_memory #(.DEPTH(DEPTH), .NUM_READ_PORTS(NUM_READ_PORTS+1))
             mem (
-                .clk (clk), .rst (rst),
+                .clk (clk),
                 .toggle(_toggle[j]),
                 .toggle_id(_toggle_addr[j]),
                 .read_id(_read_addr),
diff --git a/core/instruction_metadata_and_id_management.sv b/core/instruction_metadata_and_id_management.sv
index daa6b88..2d4dfcd 100644
--- a/core/instruction_metadata_and_id_management.sv
+++ b/core/instruction_metadata_and_id_management.sv
@@ -311,7 +311,6 @@ module instruction_metadata_and_id_management
     ) id_waiting_for_writeback_toggle_mem_set
     (
         .clk (clk),
-        .rst (rst),
         .init_clear (gc.init_clear),
         .toggle (id_waiting_toggle),
         .toggle_addr (id_waiting_toggle_addr),
diff --git a/core/mmu/mmu.sv b/core/mmu/mmu.sv
index fcc52da..100834c 100644
--- a/core/mmu/mmu.sv
+++ b/core/mmu/mmu.sv
@@ -22,9 +22,6 @@
 
 module mmu
 
-    import cva5_config::*;
-    import riscv_types::*;
-    import cva5_types::*;
     import csr_types::*;
 
     (
diff --git a/core/register_file.sv b/core/register_file.sv
index a3a78a0..5720d82 100644
--- a/core/register_file.sv
+++ b/core/register_file.sv
@@ -100,7 +100,6 @@ module register_file
     ) id_inuse_toggle_mem_set
     (
         .clk (clk),
-        .rst (rst),
         .init_clear (gc.init_clear),
         .toggle (toggle),
         .toggle_addr (toggle_addr),