diff --git a/core/lfsr.sv b/core/lfsr.sv
index ce14c23..8c2bfcc 100644
--- a/core/lfsr.sv
+++ b/core/lfsr.sv
@@ -25,7 +25,7 @@ module lfsr
 
     #(
         parameter WIDTH = 3,
-        parameter FULL_RANGE = 1
+        parameter NEEDS_RESET = 1
     )
     (
         input logic clk,
@@ -81,21 +81,23 @@ module lfsr
     logic feedback;
     ////////////////////////////////////////////////////
     //Implementation
-
-    generate begin
+    generate if (WIDTH == 2) begin
+        assign feedback = ~value[WIDTH-1];
+    end
+    else begin
         for (genvar i = 0; i < NUM_TAPS[TAPS_INDEX]; i++) begin
             assign feedback_input[i] = value[TAPS[TAPS_INDEX][i + 1] - 1];
         end
         //XNOR of taps and range extension to include all ones
-        if (FULL_RANGE)
-            assign feedback = (~^feedback_input) ^ |value[WIDTH-2:0];
-        else
-            assign feedback = (~^feedback_input);
-    end endgenerate
+        assign feedback = (~^feedback_input) ^ |value[WIDTH-2:0];
+    end
+    endgenerate
 
     initial value = 0;
     always_ff @ (posedge clk) begin
-        if (en)
+        if (NEEDS_RESET & rst)
+            value <= '0;
+        else if (en)
             value <= {value[WIDTH-2:0], feedback};
     end
 
diff --git a/core/taiga_fifo.sv b/core/taiga_fifo.sv
index 3286ba4..1cc7cd5 100755
--- a/core/taiga_fifo.sv
+++ b/core/taiga_fifo.sv
@@ -104,13 +104,13 @@ module taiga_fifo
         assign fifo.valid = inflight_count[LOG2_FIFO_DEPTH];
         assign fifo.full = fifo.valid & ~|inflight_count[LOG2_FIFO_DEPTH-1:0];
 
-        lfsr #(.WIDTH(LOG2_FIFO_DEPTH))
+        lfsr #(.WIDTH(LOG2_FIFO_DEPTH), .NEEDS_RESET(1))
         lfsr_read_index (
             .clk (clk),.rst (rst),
             .en(fifo.pop),
             .value(read_index)
         );
-        lfsr #(.WIDTH(LOG2_FIFO_DEPTH))
+        lfsr #(.WIDTH(LOG2_FIFO_DEPTH), .NEEDS_RESET(1))
         lfsr_write_index (
             .clk (clk), .rst (rst),
             .en(fifo.push),
diff --git a/core/tlb_lut_ram.sv b/core/tlb_lut_ram.sv
index a6552a8..d1e5f2b 100755
--- a/core/tlb_lut_ram.sv
+++ b/core/tlb_lut_ram.sv
@@ -74,7 +74,7 @@ module tlb_lut_ram
     //LUTRAM-based
     //Reset is performed sequentially, coordinated by the gc unit
 
-    lfsr #(.WIDTH($clog2(DEPTH)))
+    lfsr #(.WIDTH($clog2(DEPTH)), .NEEDS_RESET(0))
     lfsr_counter (
         .clk (clk), .rst (rst),
         .en(gc_tlb_flush),
diff --git a/core/toggle_memory_set.sv b/core/toggle_memory_set.sv
index 90cccb3..6b5301e 100644
--- a/core/toggle_memory_set.sv
+++ b/core/toggle_memory_set.sv
@@ -53,7 +53,7 @@ module toggle_memory_set
     logic [$clog2(DEPTH)-1:0] clear_index;
 
     //counter for indexing through memories for post-reset clearing/initialization
-    lfsr #(.WIDTH($clog2(DEPTH)))
+    lfsr #(.WIDTH($clog2(DEPTH)), .NEEDS_RESET(0))
     lfsr_counter (
         .clk (clk), .rst (rst),
         .en(init_clear),