diff --git a/core/fetch.sv b/core/fetch.sv
index 8e200b1..74d17d0 100755
--- a/core/fetch.sv
+++ b/core/fetch.sv
@@ -47,6 +47,7 @@ module fetch(
 
         //Instruction Metadata
         output logic early_branch_flush,
+        output logic early_branch_flush_ras_adjust,
         output logic [31:0] if_pc,
         output logic [31:0] fetch_instruction,
 
@@ -80,6 +81,7 @@ module fetch(
 
     typedef struct packed{
         logic is_predicted_branch_or_jump;
+        logic is_branch;
         logic address_valid;
         logic mmu_fault;
         logic [NUM_SUB_UNITS_W-1:0] subunit_id;
@@ -179,6 +181,7 @@ module fetch(
         .int_out    (fetch_attr_next.subunit_id)
     );
     assign fetch_attr_next.is_predicted_branch_or_jump = bp.use_prediction;
+    assign fetch_attr_next.is_branch = bp.use_prediction & bp.is_branch;
     assign fetch_attr_next.address_valid = address_valid;
     assign fetch_attr_next.mmu_fault = tlb.is_fault;
 
@@ -245,13 +248,14 @@ module fetch(
     assign fetch_metadata.error_code = fetch_attr.mmu_fault ? FETCH_PAGE_FAULT : FETCH_ACCESS_FAULT;
 
     assign fetch_instruction = unit_data_array[fetch_attr.subunit_id];
-    assign fetch_complete = ((fetch_attr_fifo.valid & ~valid_fetch_result) | (|unit_data_valid) & (~early_branch_flush));//allow instruction to propagate to decode if address is invalid
+    assign fetch_complete = (fetch_attr_fifo.valid & ~valid_fetch_result) | (|unit_data_valid);//allow instruction to propagate to decode if address is invalid
 
     ////////////////////////////////////////////////////
     //Branch Predictor correction
     logic is_branch_or_jump;
     assign is_branch_or_jump = fetch_instruction[6:2] inside {JAL_T, JALR_T, BRANCH_T};
     assign early_branch_flush = (valid_fetch_result & (|unit_data_valid)) & fetch_attr.is_predicted_branch_or_jump & (~is_branch_or_jump);
+    assign early_branch_flush_ras_adjust = (valid_fetch_result & (|unit_data_valid)) & fetch_attr.is_branch & (~is_branch_or_jump);
     generate if (ENABLE_TRACE_INTERFACE) begin
         assign tr_early_branch_correction = early_branch_flush;
     end endgenerate
diff --git a/core/instruction_metadata_and_id_management.sv b/core/instruction_metadata_and_id_management.sv
index 85a37f8..5b035b4 100644
--- a/core/instruction_metadata_and_id_management.sv
+++ b/core/instruction_metadata_and_id_management.sv
@@ -191,7 +191,7 @@ module instruction_metadata_and_id_management
             decode_id <= 0;
         end
         else begin
-            pc_id <= next_pc_id_base + LOG2_MAX_IDS'({pc_id_assigned & (~gc_fetch_flush) & (~early_branch_flush)});
+            pc_id <= next_pc_id_base + LOG2_MAX_IDS'({pc_id_assigned & (~gc_fetch_flush)});
             fetch_id <= next_fetch_id_base + LOG2_MAX_IDS'({fetch_complete & ~gc_fetch_flush});
             decode_id <= decode_id + LOG2_MAX_IDS'({decode_advance & ~gc_fetch_flush});
         end
diff --git a/core/ras.sv b/core/ras.sv
index 817ddf4..789852b 100755
--- a/core/ras.sv
+++ b/core/ras.sv
@@ -28,6 +28,7 @@ module ras (
         input logic clk,
         input logic rst,
         input logic gc_fetch_flush,
+        input logic early_branch_flush_ras_adjust,
         ras_interface.self ras
         );
 
@@ -46,12 +47,12 @@ module ras (
     //On a speculative branch, save the current stack pointer
     //Restored if branch is misspredicted (gc_fetch_flush)
     taiga_fifo #(.DATA_WIDTH(RAS_DEPTH_W), .FIFO_DEPTH(MAX_IDS))
-        read_index_fifo (.clk, .rst(rst | gc_fetch_flush), .fifo(ri_fifo));
+        read_index_fifo (.clk, .rst(rst | gc_fetch_flush | early_branch_flush_ras_adjust), .fifo(ri_fifo));
 
     assign ri_fifo.data_in = read_index;
     assign ri_fifo.push = ras.branch_fetched;
     assign ri_fifo.potential_push = ras.branch_fetched;
-    assign ri_fifo.pop = ras.branch_retired;
+    assign ri_fifo.pop = ras.branch_retired & ri_fifo.valid; //Prevent popping from fifo if reset due to early_branch_flush_ras_adjust
 
     always_ff @ (posedge clk) begin
         if (ras.push)
diff --git a/core/taiga.sv b/core/taiga.sv
index 6c49281..5f80882 100755
--- a/core/taiga.sv
+++ b/core/taiga.sv
@@ -95,6 +95,7 @@ module taiga (
     logic fetch_complete;
     logic [31:0] fetch_instruction;
     logic early_branch_flush;
+    logic early_branch_flush_ras_adjust;
     fetch_metadata_t fetch_metadata;
         //Decode stage
     logic decode_advance;
@@ -263,6 +264,7 @@ module taiga (
         .bp                       (bp),
         .ras                      (ras),
         .early_branch_flush (early_branch_flush),
+        .early_branch_flush_ras_adjust (early_branch_flush_ras_adjust),
         .if_pc                    (if_pc),
         .fetch_instruction        (fetch_instruction),                                
         .instruction_bram         (instruction_bram), 
@@ -288,6 +290,7 @@ module taiga (
         .clk              (clk),
         .rst              (rst),
         .gc_fetch_flush   (gc_fetch_flush),
+        .early_branch_flush_ras_adjust (early_branch_flush_ras_adjust),
         .ras              (ras)
     );