diff --git a/core/mmu/mmu.sv b/core/mmu/mmu.sv
index b0e7f1a..3d48842 100644
--- a/core/mmu/mmu.sv
+++ b/core/mmu/mmu.sv
@@ -182,11 +182,9 @@ module mmu
 
     ////////////////////////////////////////////////////
     //Assertions
-    `ifdef ENABLE_SIMULATION_ASSERTIONS
-        mmu_spurious_l1_response:
-            assert property (@(posedge clk) disable iff (rst) (mem.rvalid) |-> (state[WAIT_REQUEST_1] | state[WAIT_REQUEST_2]))
-            else $error("mmu recieved response without a request");
-    `endif
+    mmu_spurious_l1_response:
+        assert property (@(posedge clk) disable iff (rst) (mem.rvalid) |-> (state[WAIT_REQUEST_1] | state[WAIT_REQUEST_2]))
+        else $error("mmu recieved response without a request");
 
     //TLB request remains high until it recieves a response from the MMU unless
     //the transaction is aborted.  As such, if TLB request is low and we are not in the
diff --git a/core/types_and_interfaces/cva5_config.sv b/core/types_and_interfaces/cva5_config.sv
index 7d5bd5b..e6f9f24 100644
--- a/core/types_and_interfaces/cva5_config.sv
+++ b/core/types_and_interfaces/cva5_config.sv
@@ -391,17 +391,4 @@ package cva5_config;
         GC_EXCEPTION = 4
     } exception_sources_t;
 
-    ////////////////////////////////////////////////////
-    //Debug Parameters
-
-    //To enable assertions specific to formal debug, uncomment or set in tool flow
-    //`define ENABLE_FORMAL_ASSERTIONS
-
-    //To enable assertions specific to simulation (verilator), uncomment or set in tool flow
-    //`define ENABLE_SIMULATION_ASSERTIONS
-
-    //When no exceptions are expected in a simulation, turn on this flag
-    //to convert any exceptions into assertions
-    localparam DEBUG_CONVERT_EXCEPTIONS_INTO_ASSERTIONS = 0;
-
 endpackage
diff --git a/tools/cva5.mak b/tools/cva5.mak
index bcb4bc4..eb32d12 100644
--- a/tools/cva5.mak
+++ b/tools/cva5.mak
@@ -53,7 +53,7 @@ lint-full:
 #Build CVA5 Sim
 $(CVA5_SIM): $(CVA5_HW_SRCS) $(CVA5_SIM_SRCS)
 	mkdir -p $(CVA5_SIM_DIR)
-	verilator --cc --exe --Mdir $(CVA5_SIM_DIR) -DENABLE_SIMULATION_ASSERTIONS --assert \
+	verilator --cc --exe --Mdir $(CVA5_SIM_DIR) --assert \
 		-o cva5-sim \
 		$(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) \
 		$(CVA5_SIM_SRCS) \