diff --git a/examples/nexys/nexys_config.sv b/examples/nexys/nexys_config.sv
index d60f47e..0d51116 100644
--- a/examples/nexys/nexys_config.sv
+++ b/examples/nexys/nexys_config.sv
@@ -41,7 +41,7 @@ package nexys_config;
             MUL : 1,
             DIV : 1,
             CSR : 1,
-            FPU : 0,
+            FPU : 1,
             CUSTOM : 0,
             BR : 1,
             IEC : 1
@@ -124,10 +124,10 @@ package nexys_config;
             L : 32'h00000000, 
             H : 32'hFFFFFFFF
         },
-        INCLUDE_PERIPHERAL_BUS : 0,
+        INCLUDE_PERIPHERAL_BUS : 1,
         PERIPHERAL_BUS_ADDR : '{
-            L : 32'h00000000,
-            H : 32'hFFFFFFFF
+            L : 32'h60000000,
+            H : 32'h6FFFFFFF
         },
         PERIPHERAL_BUS_TYPE : AXI_BUS,
         //Branch Predictor Options
diff --git a/examples/nexys/nexys_sim.sv b/examples/nexys/nexys_sim.sv
index 59b195d..63d7b26 100644
--- a/examples/nexys/nexys_sim.sv
+++ b/examples/nexys/nexys_sim.sv
@@ -102,11 +102,6 @@ module cva5_sim
         output logic store_queue_empty
     );
 
-    parameter SCRATCH_MEM_KB = 128;
-    parameter MEM_LINES = (SCRATCH_MEM_KB*1024)/4;
-    parameter UART_ADDR = 32'h88001000;
-    parameter UART_ADDR_LINE_STATUS = 32'h88001014;
-
     interrupt_t s_interrupt;
     interrupt_t m_interrupt;
     logic[63:0] mtime;
@@ -140,14 +135,50 @@ module cva5_sim
     l1_to_axi  arb(.*, .cpu(l2), .axi(axi));
     cva5 #(.CONFIG(NEXYS_CONFIG)) cpu(.*);
 
-    initial begin
-        write_uart = 0;
-        uart_byte = 0;
-    end
     //Capture writes to UART
     always_ff @(posedge clk) begin
-        write_uart <= (axi.wvalid && axi.wready && axi.awaddr == UART_ADDR);
-        uart_byte <= axi.wdata[7:0];
+        if (rst) begin
+            m_axi.awready <= 1;
+            m_axi.wready <= 0;
+            m_axi.bvalid <= 0;
+            write_uart <= 0;
+        end
+        else begin
+            write_uart <= 0;
+            if (m_axi.awvalid & m_axi.awready) begin
+                m_axi.awready <= 0;
+                m_axi.wready <= 1;
+            end
+            else if (m_axi.wvalid & m_axi.wready) begin
+                m_axi.wready <= 0;
+                m_axi.bvalid <= 1;
+                write_uart <= 1;
+            end
+            else if (m_axi.bvalid & m_axi.bready) begin
+                m_axi.bvalid <= 0;
+                m_axi.awready <= 1;
+            end
+        end
+        uart_byte <= m_axi.wdata[7:0];
+    end
+
+    //Simulate UART read response
+    assign m_axi.rdata = 32'hFFFFFF21;
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            m_axi.arready <= 1;
+            m_axi.rvalid <= 0;
+        end
+        else begin
+            if (m_axi.arvalid & m_axi.arready) begin
+                m_axi.arready <= 0;
+                m_axi.rvalid <= 1;
+            end
+            else if (m_axi.rvalid & m_axi.rready) begin
+                m_axi.rvalid <= 0;
+                m_axi.arready <= 1;
+            end
+        end
     end
 
     ////////////////////////////////////////////////////