diff --git a/core/toggle_memory.sv b/core/toggle_memory.sv
index 44b9d3b..9dd9c36 100644
--- a/core/toggle_memory.sv
+++ b/core/toggle_memory.sv
@@ -26,7 +26,8 @@ module toggle_memory
     import taiga_types::*;
     
     # (
-        parameter DEPTH = 8
+        parameter DEPTH = 8,
+        parameter NUM_READ_PORTS = 2
     )
     (
         input logic clk,
@@ -35,8 +36,8 @@ module toggle_memory
         input logic toggle,
         input logic [$clog2(DEPTH)-1:0] toggle_id,
 
-        input logic [$clog2(DEPTH)-1:0] read_id,
-        output logic read_data
+        input logic [$clog2(DEPTH)-1:0] read_id [NUM_READ_PORTS],
+        output logic read_data [NUM_READ_PORTS]
     );
     ////////////////////////////////////////////////////
     //Implementation
@@ -46,8 +47,14 @@ module toggle_memory
     always_ff @ (posedge clk) begin
         id_toggle_memory[toggle_id] <= toggle ^ id_toggle_memory[toggle_id];
     end
+    
+    generate
+    for (genvar i = 0; i < NUM_READ_PORTS; i++) begin : read_port_gen
+        assign read_data[i] = id_toggle_memory[read_id[i]];
+    end
+    endgenerate
+    
 
-    assign read_data = id_toggle_memory[read_id];
 
     ////////////////////////////////////////////////////
     //End of Implementation
diff --git a/core/toggle_memory_set.sv b/core/toggle_memory_set.sv
index 9d19f42..5ef430a 100644
--- a/core/toggle_memory_set.sv
+++ b/core/toggle_memory_set.sv
@@ -45,10 +45,11 @@ module toggle_memory_set
     );
     ////////////////////////////////////////////////////
     //Implementation
-    logic [$clog2(DEPTH)-1:0] _toggle_addr [NUM_WRITE_PORTS];
-    logic _toggle [NUM_WRITE_PORTS];
-    logic [$clog2(DEPTH)-1:0] _read_addr [NUM_READ_PORTS];
-    logic read_data [NUM_WRITE_PORTS][NUM_READ_PORTS];
+    logic [$clog2(DEPTH)-1:0] _toggle_addr [NUM_WRITE_PORTS+1];
+    logic _toggle [NUM_WRITE_PORTS+1];
+    logic [$clog2(DEPTH)-1:0] _read_addr [NUM_READ_PORTS+1];
+    logic read_data [NUM_WRITE_PORTS+1][NUM_READ_PORTS+1];
+    logic _in_use [NUM_READ_PORTS+1];
     logic [$clog2(DEPTH)-1:0] clear_index;
 
     //counter for indexing through memories for post-reset clearing/initialization
@@ -61,41 +62,45 @@ module toggle_memory_set
     
     //muxing of read and write ports to support post-reset clearing/initialization
     always_comb begin
-        _toggle_addr = toggle_addr;
-        _read_addr = read_addr;
-        _toggle = toggle;
+        _toggle_addr[0:NUM_WRITE_PORTS-1] = toggle_addr;
+        _toggle[0:NUM_WRITE_PORTS-1] = toggle;
+        _read_addr[0:NUM_READ_PORTS-1] = read_addr;
         
-        _toggle_addr[WRITE_INDEX_FOR_RESET] = init_clear ? clear_index : toggle_addr[WRITE_INDEX_FOR_RESET];
-        _read_addr[READ_INDEX_FOR_RESET] = init_clear ? clear_index : read_addr[READ_INDEX_FOR_RESET];
-        _toggle[WRITE_INDEX_FOR_RESET] = init_clear ? in_use[READ_INDEX_FOR_RESET] : _toggle[WRITE_INDEX_FOR_RESET];
+        _toggle_addr[NUM_WRITE_PORTS] = clear_index;
+        _toggle[NUM_WRITE_PORTS] = init_clear & _in_use[NUM_READ_PORTS];
+        _read_addr[NUM_READ_PORTS] = clear_index;
     end
 
 
     //Instantiation of NUM_READ_PORTS*NUM_WRITE_PORTS dual-ported single-bit wide toggle memories
     genvar i, j;
     generate
-    for (i = 0; i < NUM_READ_PORTS; i++) begin : read_port_gen
-        for (j = 0; j < NUM_WRITE_PORTS; j++) begin : write_port_gen
-            toggle_memory #(.DEPTH(DEPTH)) mem (
+        for (j = 0; j < NUM_WRITE_PORTS+1; j++) begin : write_port_gen
+            toggle_memory #(.DEPTH(DEPTH), .NUM_READ_PORTS(NUM_READ_PORTS+1))
+            mem (
                 .clk (clk), .rst (rst),
                 .toggle(_toggle[j]),
                 .toggle_id(_toggle_addr[j]),
-                .read_id(_read_addr[i]),
-                .read_data(read_data[j][i])
+                .read_id(_read_addr),
+                .read_data(read_data[j])
             );
         end
-    end
     endgenerate
 
     //In-use determination.  XOR of all write blocks for each read address
     always_comb begin
-        in_use = '{default: 0};
-        for (int i = 0;  i < NUM_READ_PORTS; i++) begin
-            for (int j = 0; j < NUM_WRITE_PORTS; j++) begin
-                in_use[i] ^= read_data[j][i];
+        _in_use = '{default: 0};
+        for (int i = 0;  i < NUM_READ_PORTS+1; i++) begin
+            for (int j = 0; j < NUM_WRITE_PORTS+1; j++) begin
+                _in_use[i] ^= read_data[j][i];
             end
         end
+        for (int i = 0;  i < NUM_READ_PORTS; i++) begin
+            in_use[i] = _in_use[i];
+        end
     end
+    
+    
 
     ////////////////////////////////////////////////////
     //End of Implementation