diff --git a/core/dcache.sv b/core/dcache.sv
index 24e0a9c..bbfa2dc 100755
--- a/core/dcache.sv
+++ b/core/dcache.sv
@@ -261,7 +261,7 @@ module dcache(
 
     ////////////////////////////////////////////////////
     //Pipeline Advancement
-    assign line_complete = (l1_response.data_valid && (word_count == (DCACHE_LINE_W-1))); //covers load, LR, AMO
+    assign line_complete = (l1_response.data_valid && (word_count == $clog2(DCACHE_LINE_W)'(DCACHE_LINE_W-1))); //covers load, LR, AMO
     assign store_complete = l1_request.ack & stage2_store & ~stage2_amo.is_sc;
 
     //read miss complete includes store conditional complete
diff --git a/core/fetch.sv b/core/fetch.sv
index 918ce3b..57e3c6f 100755
--- a/core/fetch.sv
+++ b/core/fetch.sv
@@ -150,6 +150,7 @@ module fetch(
 
     ////////////////////////////////////////////////////
     //Subunit Interfaces
+    logic cache_address_match;
     generate
         for (i = 0; i < NUM_SUB_UNITS; i++) begin
             assign unit_ready[i] = fetch_sub[i].ready;
@@ -166,12 +167,13 @@ module fetch(
 
     generate if (USE_I_SCRATCH_MEM) begin
         ibram i_bram (.*, .fetch_sub(fetch_sub[BRAM_ID]));
-        assign sub_unit_address_match[BRAM_ID] = USE_ICACHE ? ~sub_unit_address_match[ICACHE_ID] : 1'b1;
+        assign sub_unit_address_match[BRAM_ID] = USE_ICACHE ? ~cache_address_match : 1'b1;
     end
     endgenerate
     generate if (USE_ICACHE) begin
         icache i_cache (.*, .fetch_sub(fetch_sub[ICACHE_ID]));
-        assign sub_unit_address_match[ICACHE_ID] = tlb.physical_address[31:32-MEMORY_BIT_CHECK] == MEMORY_ADDR_L[31:32-MEMORY_BIT_CHECK];
+        assign cache_address_match = tlb.physical_address[31:32-MEMORY_BIT_CHECK] == MEMORY_ADDR_L[31:32-MEMORY_BIT_CHECK];
+        assign sub_unit_address_match[ICACHE_ID] = cache_address_match;
 
         set_clr_reg_with_rst #(.SET_OVER_CLR(1), .WIDTH(1), .RST_VALUE(0)) stage2_valid_m (
           .clk, .rst(flush_or_rst),
diff --git a/core/icache.sv b/core/icache.sv
index b353b7e..c91e8af 100755
--- a/core/icache.sv
+++ b/core/icache.sv
@@ -177,7 +177,7 @@ module icache(
     /*************************************
      * Pipeline Advancement
      *************************************/
-    assign  line_complete = (l1_response.data_valid && (word_count == (ICACHE_LINE_W-1)));
+    assign  line_complete = (l1_response.data_valid && (word_count == $clog2(ICACHE_LINE_W)'(ICACHE_LINE_W-1)));
 
     always_ff @ (posedge clk) begin
         if (rst)