diff --git a/core/csr_regs.sv b/core/csr_unit.sv
similarity index 100%
rename from core/csr_regs.sv
rename to core/csr_unit.sv
diff --git a/core/gc_unit.sv b/core/gc_unit.sv
index 68fa932..54ca01c 100644
--- a/core/gc_unit.sv
+++ b/core/gc_unit.sv
@@ -133,7 +133,6 @@ module gc_unit
     typedef enum {RST_STATE, PRE_CLEAR_STATE, INIT_CLEAR_STATE, IDLE_STATE, TLB_CLEAR_STATE, IQ_DRAIN} gc_state;
     gc_state state;
     gc_state next_state;
-    gc_state prev_state;
 
     logic init_clear_done;
     logic tlb_clear_done;
@@ -206,13 +205,6 @@ module gc_unit
             state <= next_state;
     end
 
-    always @(posedge clk) begin
-        if (rst)
-            prev_state <= RST_STATE;
-        else
-            prev_state <= state;
-    end
-
     always_comb begin
         next_state = state;
         case (state)
@@ -308,7 +300,7 @@ module gc_unit
 
     ////////////////////////////////////////////////////
     //CSR registers
-    csr_regs # (.CONFIG(CONFIG))
+    csr_unit # (.CONFIG(CONFIG))
     csr_registers (
         .clk(clk), .rst(rst),
         .csr_inputs(csr_inputs),
diff --git a/tools/taiga_compile_order b/tools/taiga_compile_order
index 4ca0c3a..f9c99cb 100644
--- a/tools/taiga_compile_order
+++ b/tools/taiga_compile_order
@@ -11,7 +11,7 @@ local_memory/local_mem.sv
 core/interfaces.sv  
 core/external_interfaces.sv  
 
-core/csr_regs.sv  
+core/csr_unit.sv  
 core/gc_unit.sv  
 
 core/branch_comparator.sv