diff --git a/core/decode_and_issue.sv b/core/decode_and_issue.sv index 50b783f..c1e764b 100755 --- a/core/decode_and_issue.sv +++ b/core/decode_and_issue.sv @@ -177,7 +177,7 @@ module decode_and_issue ( assign unit_needed[BRANCH_UNIT_ID] = opcode_trim inside {BRANCH_T, JAL_T, JALR_T}; assign unit_needed[ALU_UNIT_WB_ID] = ((opcode_trim == ARITH_T) && ~decode.instruction[25]) || (opcode_trim inside {ARITH_IMM_T, AUIPC_T, LUI_T, JAL_T, JALR_T}); assign unit_needed[LS_UNIT_WB_ID] = opcode_trim inside {LOAD_T, STORE_T, AMO_T}; - assign unit_needed[GC_UNIT_ID] = opcode_trim inside {SYSTEM_T, FENCE_T}; + assign unit_needed[GC_UNIT_WB_ID] = opcode_trim inside {SYSTEM_T, FENCE_T}; assign mult_div_op = (opcode_trim == ARITH_T) && decode.instruction[25]; generate if (USE_MUL) @@ -475,11 +475,11 @@ module decode_and_issue ( assign gc_inputs.instruction = issue.instruction; assign gc_inputs.is_csr = is_csr_r; assign gc_inputs.is_fence = is_fence; - assign gc_inputs.is_i_fence = ENABLE_M_MODE & issue_to[GC_UNIT_ID] & is_ifence_r; + assign gc_inputs.is_i_fence = ENABLE_M_MODE & issue_to[GC_UNIT_WB_ID] & is_ifence_r; assign gc_inputs.rs1 = rs_data[RS1]; assign gc_inputs.rs2 = rs_data[RS2]; - assign gc_flush_required = ENABLE_M_MODE && issue_to[GC_UNIT_ID] && potential_flush; + assign gc_flush_required = ENABLE_M_MODE && issue_to[GC_UNIT_WB_ID] && potential_flush; //////////////////////////////////////////////////// //Mul unit inputs diff --git a/core/gc_unit.sv b/core/gc_unit.sv index 7dd333c..17b640e 100644 --- a/core/gc_unit.sv +++ b/core/gc_unit.sv @@ -84,12 +84,9 @@ module gc_unit( output logic [31:0] gc_fetch_pc, - //Write-back to Load-Store Unit - output logic[31:0] csr_rd, - output id_t csr_id, - output logic csr_done, - input logic ls_is_idle - ); + input logic ls_is_idle, + unit_writeback_interface.unit wb + ); //Largest depth for TLBs localparam int TLB_CLEAR_DEPTH = (DTLB_DEPTH > ITLB_DEPTH) ? DTLB_DEPTH : ITLB_DEPTH; @@ -169,7 +166,7 @@ module gc_unit( logic csr_ready_to_complete; logic csr_ready_to_complete_r; id_t instruction_id; - + id_t csr_id; //////////////////////////////////////////////////// //Implementation //Input registering @@ -373,8 +370,12 @@ module gc_unit( end end - assign csr_done = csr_ready_to_complete_r; - assign csr_rd = wb_csr; + //////////////////////////////////////////////////// + //Output + assign wb.rd = wb_csr; + assign wb.done = csr_ready_to_complete_r; + assign wb.id = csr_id; + //////////////////////////////////////////////////// //End of Implementation //////////////////////////////////////////////////// diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 6b65d88..adeb3f5 100755 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -57,9 +57,6 @@ module load_store_unit ( input wb_packet_t wb_snoop, //CSR support - input logic[31:0] csr_rd, - input id_t csr_id, - input logic csr_done, output logic ls_is_idle, output exception_packet_t ls_exception, @@ -382,9 +379,9 @@ endgenerate //////////////////////////////////////////////////// //Output bank - assign wb.rd = csr_done ? csr_rd : final_load_data; - assign wb.done = csr_done | load_complete; - assign wb.id = csr_done ? csr_id : stage2_attr.id; + assign wb.rd = final_load_data; + assign wb.done = load_complete; + assign wb.id = stage2_attr.id; //////////////////////////////////////////////////// //End of Implementation @@ -396,10 +393,6 @@ endgenerate assert property (@(posedge clk) disable iff (rst) load_complete |-> (load_attributes.valid && unit_data_valid[stage2_attr.subunit_id])) else $error("Spurious load complete detected!"); - csr_load_conflict_assertion: - assert property (@(posedge clk) disable iff (rst) csr_done |-> ls_is_idle) - else $error("CSR read completed without ls being idle"); - `ifdef ENABLE_SIMULATION_ASSERTIONS invalid_ls_address_assertion: assert property (@(posedge clk) disable iff (rst) issue_request |-> |sub_unit_address_match) diff --git a/core/taiga.sv b/core/taiga.sv index a455a22..7c0b84e 100755 --- a/core/taiga.sv +++ b/core/taiga.sv @@ -131,10 +131,6 @@ module taiga ( logic gc_supress_writeback; logic gc_tlb_flush; logic [31:0] gc_fetch_pc; - - logic[31:0] csr_rd; - id_t csr_id; - logic csr_done; logic ls_is_idle; //Decode Unit and Fetch Unit @@ -445,11 +441,8 @@ module taiga ( .m_wishbone (m_wishbone), .data_bram (data_bram), .store_complete (store_complete), - .store_id (store_id), - .wb_snoop (wb_snoop), - .csr_rd (csr_rd), - .csr_id (csr_id), - .csr_done (csr_done), + .store_id (store_id), + .wb_snoop (wb_snoop), .ls_is_idle (ls_is_idle), .ls_exception (ls_exception), .ls_exception_is_store (ls_exception_is_store), @@ -487,7 +480,7 @@ module taiga ( gc_unit gc_unit_block ( .clk (clk), .rst (rst), - .issue (unit_issue[GC_UNIT_ID]), + .issue (unit_issue[GC_UNIT_WB_ID]), .gc_inputs (gc_inputs), .gc_flush_required (gc_flush_required), .branch_flush (branch_flush), @@ -518,10 +511,8 @@ module taiga ( .gc_supress_writeback (gc_supress_writeback), .gc_tlb_flush (gc_tlb_flush), .gc_fetch_pc (gc_fetch_pc), - .csr_rd (csr_rd), - .csr_id (csr_id), - .csr_done (csr_done), - .ls_is_idle (ls_is_idle) + .ls_is_idle (ls_is_idle), + .wb (unit_wb[GC_UNIT_WB_ID]) ); generate if (USE_MUL) diff --git a/core/taiga_config.sv b/core/taiga_config.sv index 9507d5f..219fccc 100755 --- a/core/taiga_config.sv +++ b/core/taiga_config.sv @@ -31,12 +31,12 @@ package taiga_config; //Enable Machine level privilege spec localparam ENABLE_M_MODE = 1; //Enable Supervisor level privilege spec - localparam ENABLE_S_MODE = 0; + localparam ENABLE_S_MODE = 1; //Enable User level privilege spec - localparam ENABLE_U_MODE = 0; + localparam ENABLE_U_MODE = 1; localparam MACHINE_IMPLEMENTATION_ID = 0; - localparam CPU_ID = 0;//32-bit value + localparam CPU_ID = 0;//32-bicd ..t value //CSR counter width (33-64 bits): 48-bits --> 32 days @ 100MHz localparam COUNTER_W = 33; @@ -183,16 +183,17 @@ package taiga_config; //////////////////////////////////////////////////// //Write-Back Unit IDs - localparam NUM_WB_UNITS = 2 + USE_MUL + USE_DIV;//ALU and LS - localparam NUM_UNITS = NUM_WB_UNITS + 2;//Branch and CSRs + localparam NUM_WB_UNITS = 3 + USE_MUL + USE_DIV;//ALU and LS and CSR + localparam NUM_UNITS = NUM_WB_UNITS + 1;//Branch localparam ALU_UNIT_WB_ID = 0; localparam LS_UNIT_WB_ID = 1; localparam DIV_UNIT_WB_ID = LS_UNIT_WB_ID + USE_DIV; localparam MUL_UNIT_WB_ID = DIV_UNIT_WB_ID + USE_MUL; + localparam GC_UNIT_WB_ID = MUL_UNIT_WB_ID + 1; + //Non-writeback units - localparam BRANCH_UNIT_ID = MUL_UNIT_WB_ID + 1; - localparam GC_UNIT_ID = BRANCH_UNIT_ID + 1; + localparam BRANCH_UNIT_ID = GC_UNIT_WB_ID + 1; //////////////////////////////////////////////////// //Debug Parameters