!Feature
next_elt_id: 4
name: CVA6_Machine_mode_RO_CSRs(mvendorid, marchid, mimpid, mhartid)
id: 1
display_order: 1
subfeatures: !!omap
- 000_Power-on-reset (POR) values of CSR: !Subfeature
    name: 000_Power-on-reset (POR) values of CSR
    tag: VP_CSR_VERIFICATION_F001_S000
    next_elt_id: 1
    display_order: 0
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_CSR_VERIFICATION_F001_S000_I000
        description: Upon reset,RISC-V CVA6 Machine RO(read only) CSR must initialize
          to their respective POR value.
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: Verify that the Machine RO(Read only) CSR POR value must match
          with the value specified in the RISC-V CVA6 User Manual.
        pfc: 1
        test_type: 1
        cov_method: 1
        cores: 8
        coverage_loc: ''
        comments: ''
- 001_CSR write and read operations: !Subfeature
    name: 001_CSR write and read operations
    tag: VP_CSR_VERIFICATION_F001_S001
    next_elt_id: 1
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_CSR_VERIFICATION_F001_S001_I000
        description: Check the correctness of RISCV CVA6 read only CSR by writing
          random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and confirm whether
          write into RO CSRs is possible or not.
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "1.Attempt to write a RO CSR.\n2.Check to see that an illegal
          instruction exception occurred.\n3.Immediately after returning from the
          exception handler, check to see that the CSR value is not changed."
        pfc: 1
        test_type: 1
        cov_method: 1
        cores: 8
        coverage_loc: ''
        comments: ''
- 002_CSR access in different privilege modes: !Subfeature
    name: 002_CSR access in different privilege modes
    tag: VP_CSR_VERIFICATION_F001_S002
    next_elt_id: 1
    display_order: 2
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_CSR_VERIFICATION_F001_S002_I000
        description: Accessing RISC-V Machine read only CSRs in different privilege
          modes (User, Supervisor and Machine modes).
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "1.Ensure that Machine mode read only CSRs can only be accessed
          in Machine mode according to the RISC-V specification and does not alter
          the value of the CSR.\n\n2.Verify that trying to access a Machine read only
          CSRs in an lower privilege mode raises an illegal instruction exception."
        pfc: 1
        test_type: 1
        cov_method: 1
        cores: 8
        coverage_loc: ''
        comments: ''
vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'
