!Feature
next_elt_id: 4
name: CVA6_Machine_mode_counter_csr(mcycle,mcycleh,minstret,minstreth)
id: 4
display_order: 2
subfeatures: !!omap
- 000_Power-on-reset (POR) values of CSR: !Subfeature
    name: 000_Power-on-reset (POR) values of CSR
    tag: VP_csr-access_F002_S000
    next_elt_id: 1
    display_order: 0
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_csr-access_F002_S000_I000
        description: Upon reset, RISC-V CVA6 Machine mode counter CSRs must initialize
          to their respective POR value.
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Verify that the Machine Mode counter CSR POR value must match
          with the value specified in the RISC-V CVA6 user manual.\nAs mcycle will
          increment on the posedge of each clock and minstret will increment after
          every instruction is retired. For these CSRs, the best technique to check
          reset value is by \"visual inspection\""
        pfc: 1
        test_type: 1
        cov_method: 1
        cores: 8
        coverage_loc: ''
        comments: ''
- ? "001_Counter _CSRs_functionality_checking\n"
  : !Subfeature
    name: "001_Counter _CSRs_functionality_checking\n"
    tag: VP_csr-access_F002_S001
    next_elt_id: 1
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_csr-access_F002_S001_I000
        description: "This feature pertains to the verification of functionality of
          RISC-V mcycle, mcycleh, minstret and minstreth Control Status Register (CSR).
          In a RISC-V architecture\n\n1.’mcycle’ and ‘mcycleh’ are machine-level CSRs
          that hold low 32 bits and high 32 bits respectively of the count of clock
          cycles executed by the processor.\n\n2.’minstret’ and ‘minstreth’ are also
          machine-level CSR that count the total number of instructions executed by
          the processor.\n\nThe functionality of machine mode counter CSR is being
          tested by performing two continuous reads and checking whether the value
          in the second read is greater than the value in the first read."
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "1.Verify that these CSR are properly initialized.\n2.Initiate
          a second read from the counter CSR immediately after the first read.\n3.Ensure
          that the value of the second read from counter CSR is greater than the value
          of the initial read.\n4.Confirm that Machine Mode counter CSRs are incrementing.\n
          \nNote: This algorithm is only an \"approximate test\" of the functionality
          of these CSRs."
        pfc: 1
        test_type: 1
        cov_method: 1
        cores: 8
        coverage_loc: ''
        comments: ''
- 002_CSR access in different privilege modes: !Subfeature
    name: 002_CSR access in different privilege modes
    tag: VP_csr-access_F002_S002
    next_elt_id: 1
    display_order: 2
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_csr-access_F002_S002_I000
        description: Accessing RISC-V CVA6 user Machine mode counter CSRs in different
          privilege modes (User, Supervisor and Machine modes).
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "1.Ensure that Machine mode CSRs can only be accessed in the
          Machine mode according to the RISC-V specification.\n2.Verify that trying
          to access Machine Mode CSRs in lower privilege mode raises an illegal instruction
          exception."
        pfc: 1
        test_type: 1
        cov_method: 1
        cores: 8
        coverage_loc: ''
        comments: ''
- 003_Verify the Machine mode counter CSRs behaviour after reaching maximum value: !Subfeature
    name: 003_Verify the Machine mode counter CSRs behaviour after reaching maximum
      value
    tag: VP_csr-access_F002_S003
    next_elt_id: 1
    display_order: 3
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_csr-access_F002_S003_I000
        description: check the behaviour of the RISC-V Machine mode counter CSRs when
          it reaches to maximum value.
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: Ensure that Machine mode counter CSRs is updated to reset value
          as mentioned in CVA6 user manual after reaching it to maximum value.
        pfc: 1
        test_type: 1
        cov_method: 1
        cores: 8
        coverage_loc: ''
        comments: ''
vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'
