////
  Copyright (c) 2024 OpenHW Group
  Copyright (c) 2024 Thales
  SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
  Author: Abdessamii Oukalrazqou
////

=== csr

==== Conventions

In the subsequent sections, register fields are labeled with one of the following abbreviations:

* WPRI (Writes Preserve Values, Reads Ignore Values): read/write field reserved
for future use.  For forward compatibility, implementations that do not
furnish these fields must make them read-only zero.
* WLRL (Write/Read Only Legal Values): read/write CSR field that specifies
behavior for only a subset of possible bit encodings, with other bit encodings
reserved.
* WARL (Write Any Values, Reads Legal Values): read/write CSR fields which are
only defined for a subset of bit encodings, but allow any value to be written
while guaranteeing to return a legal value whenever read.
* ROCST (Read-Only Constant): A special case of WARL field which admits only one
legal value, and therefore, behaves as a constant field that silently ignores
writes.
* ROVAR (Read-Only Variable): A special case of WARL field which can take
multiple legal values but cannot be modified by software and depends only on
the architectural state of the hart.

In particular, a register that is not internally divided
into multiple fields can be considered as containing a single field of XLEN bits.
This allows to clearly represent read-write registers holding a single legal value
(typically zero).

==== Register Summary

|===
|Address | Register Name | Privilege | Description

|0x300| `<<_MSTATUS,MSTATUS>>`|MRW|The mstatus register keeps track of and controls the hart's current operating state.
|0x301| `<<_MISA,MISA>>`|MRW|misa is a read-write register reporting the ISA supported by the hart.
|0x304| `<<_MIE,MIE>>`|MRW|The mie register is an MXLEN-bit read/write register containing interrupt enable bits.
|0x305| `<<_MTVEC,MTVEC>>`|MRW|MXLEN-bit read/write register that holds trap vector configuration.
|0x310| `<<_MSTATUSH,MSTATUSH>>`|MRW|The mstatush register keeps track of and controls the hart’s current operating state.
|0x323-0x33f| `<<_MHPMEVENT3-31,MHPMEVENT[3-31]>>`|MRW|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.
|0x340| `<<_MSCRATCH,MSCRATCH>>`|MRW|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.
|0x341| `<<_MEPC,MEPC>>`|MRW|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.
|0x342| `<<_MCAUSE,MCAUSE>>`|MRW|The mcause register stores the information regarding the trap.
|0x343| `<<_MTVAL,MTVAL>>`|MRW|The mtval is a warl register that holds the address of the instruction which caused the exception.
|0x344| `<<_MIP,MIP>>`|MRW|The mip register is an MXLEN-bit read/write register containing information on pending interrupts.
|0x3a0-0x3a1| `<<_PMPCFG0-1,PMPCFG[0-1]>>`|MRW|PMP configuration register
|0x3a2-0x3af| `<<_PMPCFG2-15,PMPCFG[2-15]>>`|MRW|PMP configuration register
|0x3b0-0x3b7| `<<_PMPADDR0-7,PMPADDR[0-7]>>`|MRW|Physical memory protection address register
|0x3b8-0x3ef| `<<_PMPADDR8-63,PMPADDR[8-63]>>`|MRW|Physical memory protection address register
|0x7c0| `<<_ICACHE,ICACHE>>`|MRW|the register controls the operation of the i-cache unit.
|0x7c1| `<<_DCACHE,DCACHE>>`|MRW|the register controls the operation of the d-cache unit.
|0xb00| `<<_MCYCLE,MCYCLE>>`|MRW|Counts the number of clock cycles executed from an arbitrary point in time.
|0xb02| `<<_MINSTRET,MINSTRET>>`|MRW|Counts the number of instructions completed from an arbitrary point in time.
|0xb03-0xb1f| `<<_MHPMCOUNTER3-31,MHPMCOUNTER[3-31]>>`|MRW|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.
|0xb80| `<<_MCYCLEH,MCYCLEH>>`|MRW|upper 32 bits of mcycle
|0xb82| `<<_MINSTRETH,MINSTRETH>>`|MRW|Upper 32 bits of minstret.
|0xb83-0xb9f| `<<_MHPMCOUNTER3-31H,MHPMCOUNTER[3-31]H>>`|MRW|The mhpmcounterh returns the upper half word in RV32I systems.
|0xf11| `<<_MVENDORID,MVENDORID>>`|MRO|32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.
|0xf12| `<<_MARCHID,MARCHID>>`|MRO|MXLEN-bit read-only register encoding the base microarchitecture of the hart.
|0xf13| `<<_MIMPID,MIMPID>>`|MRO|Provides a unique encoding of the version of the processor implementation.
|0xf14| `<<_MHARTID,MHARTID>>`|MRO|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.
|0xf15| `<<_MCONFIGPTR,MCONFIGPTR>>`|MRO|MXLEN-bit read-only register that holds the physical address of a configuration data structure.
|===

==== Register Description

[[_MSTATUS]]
===== MSTATUS

Address:: 0x300
Reset Value:: 0x00001800
Privilege:: MRW
Description:: The mstatus register keeps track of and controls the hart's current operating state.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| 0 | UIE | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts. 
| 1 | SIE | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts. 
| 2 | RESERVED_2 | 0x0 | WPRI |  | _Reserved_ 
| 3 | MIE | 0x0 | WLRL | 0x0 - 0x1 | Stores the state of the machine mode interrupts. 
| 4 | UPIE | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts prior to the trap. 
| 5 | SPIE | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts prior to the trap. 
| 6 | UBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for user mode 
| 7 | MPIE | 0x0 | WLRL | 0x0 - 0x1 | Stores the state of the machine mode interrupts prior to the trap. 
| 8 | SPP | 0x0 | ROCST | 0x0 | Stores the previous priority mode for supervisor. 
| [10:9] | RESERVED_9 | 0x0 | WPRI |  | _Reserved_ 
| [12:11] | MPP | 0x3 | WARL | 0x3 | Stores the previous priority mode for machine. 
| [14:13] | FS | 0x0 | ROCST | 0x0 | Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. 
| [16:15] | XS | 0x0 | ROCST | 0x0 | Encodes the status of additional user-mode extensions and associated state. 
| 17 | MPRV | 0x0 | ROCST | 0x0 | Modifies the privilege level at which loads and stores execute in all privilege modes. 
| 18 | SUM | 0x0 | ROCST | 0x0 | Modifies the privilege with which S-mode loads and stores access virtual memory. 
| 19 | MXR | 0x0 | ROCST | 0x0 | Modifies the privilege with which loads access virtual memory. 
| 20 | TVM | 0x0 | ROCST | 0x0 | Supports intercepting supervisor virtual-memory management operations. 
| 21 | TW | 0x0 | ROCST | 0x0 | Supports intercepting the WFI instruction. 
| 22 | TSR | 0x0 | ROCST | 0x0 | Supports intercepting the supervisor exception return instruction. 
| 23 | SPELP | 0x0 | ROCST | 0x0 | Supervisor mode previous expected-landing-pad (ELP) state. 
| [30:24] | RESERVED_24 | 0x0 | WPRI |  | _Reserved_ 
| 31 | SD | 0x0 | ROCST | 0x0 | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. 
|===

[[_MISA]]
===== MISA

Address:: 0x301
Reset Value:: 0x40001106
Privilege:: MRW
Description:: misa is a read-write register reporting the ISA supported by the hart.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [25:0] | EXTENSIONS | 0x1106 | ROCST | 0x1106 | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. 
| [29:26] | RESERVED_26 | 0x0 | WPRI |  | _Reserved_ 
| [31:30] | MXL | 0x1 | WARL | 0x1 | Encodes the native base integer ISA width. 
|===

[[_MIE]]
===== MIE

Address:: 0x304
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mie register is an MXLEN-bit read/write register containing interrupt enable bits.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| 0 | USIE | 0x0 | ROCST | 0x0 | User Software Interrupt enable. 
| 1 | SSIE | 0x0 | ROCST | 0x0 | Supervisor Software Interrupt enable. 
| 2 | VSSIE | 0x0 | ROCST | 0x0 | VS-level Software Interrupt enable. 
| 3 | MSIE | 0x0 | ROCST | 0x0 | Machine Software Interrupt enable. 
| 4 | UTIE | 0x0 | ROCST | 0x0 | User Timer Interrupt enable. 
| 5 | STIE | 0x0 | ROCST | 0x0 | Supervisor Timer Interrupt enable. 
| 6 | VSTIE | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt enable. 
| 7 | MTIE | 0x0 | WLRL | 0x0 - 0x1 | Machine Timer Interrupt enable. 
| 8 | UEIE | 0x0 | ROCST | 0x0 | User External Interrupt enable. 
| 9 | SEIE | 0x0 | ROCST | 0x0 | Supervisor External Interrupt enable. 
| 10 | VSEIE | 0x0 | ROCST | 0x0 | VS-level External Interrupt enable. 
| 11 | MEIE | 0x0 | WLRL | 0x0 - 0x1 | Machine External Interrupt enable. 
| 12 | SGEIE | 0x0 | ROCST | 0x0 | HS-level External Interrupt enable. 
| [31:13] | RESERVED_13 | 0x0 | WPRI |  | _Reserved_ 
|===

[[_MTVEC]]
===== MTVEC

Address:: 0x305
Reset Value:: 0x80010000
Privilege:: MRW
Description:: MXLEN-bit read/write register that holds trap vector configuration.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [1:0] | MODE | 0x0 | WARL | 0x0 | Vector mode. 
| [31:2] | BASE | 0x20004000 | WARL | 0x00000000 - 0x3FFFFFFF | Vector base address. 
|===

[[_MSTATUSH]]
===== MSTATUSH

Address:: 0x310
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mstatush register keeps track of and controls the hart’s current operating state.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [3:0] | RESERVED_0 | 0x0 | WPRI |  | _Reserved_ 
| 4 | SBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for supervisor mode 
| 5 | MBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for machine mode 
| 6 | GVA | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts. 
| 7 | MPV | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts. 
| 8 | RESERVED_8 | 0x0 | WPRI |  | _Reserved_ 
| 9 | MPELP | 0x0 | ROCST | 0x0 | Machine mode previous expected-landing-pad (ELP) state. 
| [31:10] | RESERVED_10 | 0x0 | WPRI |  | _Reserved_ 
|===

[[_MHPMEVENT3-31]]
===== MHPMEVENT[3-31]

Address:: 0x323-0x33f
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MHPMEVENT[I] | 0x00000000 | ROCST | 0x0 | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. 
|===

[[_MSCRATCH]]
===== MSCRATCH

Address:: 0x340
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MSCRATCH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. 
|===

[[_MEPC]]
===== MEPC

Address:: 0x341
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mepc is a warl register that must be able to hold all valid physical and virtual addresses.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MEPC | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. 
|===

[[_MCAUSE]]
===== MCAUSE

Address:: 0x342
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mcause register stores the information regarding the trap.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [30:0] | EXCEPTION_CODE | 0x0 | WLRL | 0x0 - 0x8, 0xb | Encodes the exception code. 
| 31 | INTERRUPT | 0x0 | WLRL | 0x0 - 0x1 | Indicates whether the trap was due to an interrupt. 
|===

[[_MTVAL]]
===== MTVAL

Address:: 0x343
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mtval is a warl register that holds the address of the instruction which caused the exception.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MTVAL | 0x00000000 | ROCST | 0x0 | The mtval is a warl register that holds the address of the instruction which caused the exception. 
|===

[[_MIP]]
===== MIP

Address:: 0x344
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mip register is an MXLEN-bit read/write register containing information on pending interrupts.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| 0 | USIP | 0x0 | ROCST | 0x0 | User Software Interrupt Pending. 
| 1 | SSIP | 0x0 | ROCST | 0x0 | Supervisor Software Interrupt Pending. 
| 2 | VSSIP | 0x0 | ROCST | 0x0 | VS-level Software Interrupt Pending. 
| 3 | MSIP | 0x0 | ROCST | 0x0 | Machine Software Interrupt Pending. 
| 4 | UTIP | 0x0 | ROCST | 0x0 | User Timer Interrupt Pending. 
| 5 | STIP | 0x0 | ROCST | 0x0 | Supervisor Timer Interrupt Pending. 
| 6 | VSTIP | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt Pending. 
| 7 | MTIP | 0x0 | ROVAR | 0x0 - 0x1 | Machine Timer Interrupt Pending. 
| 8 | UEIP | 0x0 | ROCST | 0x0 | User External Interrupt Pending. 
| 9 | SEIP | 0x0 | ROCST | 0x0 | Supervisor External Interrupt Pending. 
| 10 | VSEIP | 0x0 | ROCST | 0x0 | VS-level External Interrupt Pending. 
| 11 | MEIP | 0x0 | ROVAR | 0x0 - 0x1 | Machine External Interrupt Pending. 
| 12 | SGEIP | 0x0 | ROCST | 0x0 | HS-level External Interrupt Pending. 
| [31:13] | RESERVED_13 | 0x0 | WPRI |  | _Reserved_ 
|===

[[_PMPCFG0-1]]
===== PMPCFG[0-1]

Address:: 0x3a0-0x3a1
Reset Value:: 0x00000000
Privilege:: MRW
Description:: PMP configuration register

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [2:0] | PMP[I*4 +0]CFG.RWX | 0x0 | WARL | 0x0, 0x1, 0x3, 0x4, 0x5, 0x7 | PMP[I*4 +0]CFG collective R, W and X field (R is bit 0, X is bit 2)
| [5:4] | PMP[I*4 +0]CFG.A | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +0]CFG address-matching mode (A)
| 7 | PMP[I*4 +0]CFG.L | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +0]CFG entry locked (L)
| [2:0] | PMP[I*4 +1]CFG | 0x0 | WARL | 0x0, 0x1, 0x3, 0x4, 0x5, 0x7 | PMP[I*4 +1]CFG collective R, W and X field (R is bit 0, X is bit 2)
| [13:12] | PMP[I*4 +1]CFG | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +1]CFG address-matching mode (A)
| 15 | PMP[I*4 +1]CFG | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +1]CFG entry locked (L)
| [18:16] | PMP[I*4 +2]CFG | 0x0 | WARL | 0x0, 0x1, 0x3, 0x4, 0x5, 0x7 | PMP[I*4 +2]CFG collective R, W and X field (R is bit 0, X is bit 2)
| [21:20] | PMP[I*4 +2]CFG | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +2]CFG address-matching mode (A)
| 23 | PMP[I*4 +2]CFG | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +2]CFG entry locked (L)
| [26:24] | PMP[I*4 +3]CFG | 0x0 | WARL | 0x0, 0x1, 0x3, 0x4, 0x5, 0x7 | PMP[I*4 +3]CFG collective R, W and X field (R is bit 0, X is bit 2)
| [29:28] | PMP[I*4 +3]CFG | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +3]CFG address matching mode (A)
| 31 | PMP[I*4 +3]CFG | 0x0 | WARL | 0x0 - 0x1 | PMP[I*4 +3]CFG entry locked (L)
|===

[[_PMPCFG2-15]]
===== PMPCFG[2-15]

Address:: 0x3a2-0x3af
Reset Value:: 0x00000000
Privilege:: MRW
Description:: PMP configuration register

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [7:0] | PMP[I*4 +0]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits 
| [15:8] | PMP[I*4 +1]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits 
| [23:16] | PMP[I*4 +2]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits 
| [31:24] | PMP[I*4 +3]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits 
|===

[[_PMPADDR0-7]]
===== PMPADDR[0-7]

Address:: 0x3b0-0x3b7
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Physical memory protection address register

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | PMPADDR[I] | 0x00000000 | WARL | masked: & 0xFFFFFFFE \| 0x0 | Physical memory protection address register 
|===

[[_PMPADDR8-63]]
===== PMPADDR[8-63]

Address:: 0x3b8-0x3ef
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Physical memory protection address register

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | PMPADDR[I] | 0x00000000 | ROCST | 0x0 | Physical memory protection address register 
|===

[[_ICACHE]]
===== ICACHE

Address:: 0x7c0
Reset Value:: 0x00000001
Privilege:: MRW
Description:: the register controls the operation of the i-cache unit.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| 0 | ICACHE | 0x1 | RW | 0x1 | bit for cache-enable of instruction cache 
| [31:1] | RESERVED_1 | 0x0 | WPRI |  | _Reserved_ 
|===

[[_DCACHE]]
===== DCACHE

Address:: 0x7c1
Reset Value:: 0x00000001
Privilege:: MRW
Description:: the register controls the operation of the d-cache unit.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| 0 | DCACHE | 0x1 | RW | 0x1 | bit for cache-enable of data cache 
| [31:1] | RESERVED_1 | 0x0 | WPRI |  | _Reserved_ 
|===

[[_MCYCLE]]
===== MCYCLE

Address:: 0xb00
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Counts the number of clock cycles executed from an arbitrary point in time.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MCYCLE | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of clock cycles executed from an arbitrary point in time. 
|===

[[_MINSTRET]]
===== MINSTRET

Address:: 0xb02
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Counts the number of instructions completed from an arbitrary point in time.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MINSTRET | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of instructions completed from an arbitrary point in time. 
|===

[[_MHPMCOUNTER3-31]]
===== MHPMCOUNTER[3-31]

Address:: 0xb03-0xb1f
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MHPMCOUNTER[I] | 0x00000000 | ROCST | 0x0 | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. 
|===

[[_MCYCLEH]]
===== MCYCLEH

Address:: 0xb80
Reset Value:: 0x00000000
Privilege:: MRW
Description:: upper 32 bits of mcycle

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MCYCLEH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | upper 32 bits of mcycle 
|===

[[_MINSTRETH]]
===== MINSTRETH

Address:: 0xb82
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Upper 32 bits of minstret.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MINSTRETH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Upper 32 bits of minstret. 
|===

[[_MHPMCOUNTER3-31H]]
===== MHPMCOUNTER[3-31]H

Address:: 0xb83-0xb9f
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mhpmcounterh returns the upper half word in RV32I systems.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MHPMCOUNTER[I]H | 0x00000000 | ROCST | 0x0 | The mhpmcounterh returns the upper half word in RV32I systems. 
|===

[[_MVENDORID]]
===== MVENDORID

Address:: 0xf11
Reset Value:: 0x00000602
Privilege:: MRO
Description:: 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MVENDORID | 0x00000602 | ROCST | 0x602 | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. 
|===

[[_MARCHID]]
===== MARCHID

Address:: 0xf12
Reset Value:: 0x00000003
Privilege:: MRO
Description:: MXLEN-bit read-only register encoding the base microarchitecture of the hart.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MARCHID | 0x00000003 | ROCST | 0x3 | MXLEN-bit read-only register encoding the base microarchitecture of the hart. 
|===

[[_MIMPID]]
===== MIMPID

Address:: 0xf13
Reset Value:: 0x00000000
Privilege:: MRO
Description:: Provides a unique encoding of the version of the processor implementation.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MIMPID | 0x00000000 | ROCST | 0x0 | Provides a unique encoding of the version of the processor implementation. 
|===

[[_MHARTID]]
===== MHARTID

Address:: 0xf14
Reset Value:: 0x00000000
Privilege:: MRO
Description:: MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MHARTID | 0x00000000 | ROCST | 0x0 | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. 
|===

[[_MCONFIGPTR]]
===== MCONFIGPTR

Address:: 0xf15
Reset Value:: 0x00000000
Privilege:: MRO
Description:: MXLEN-bit read-only register that holds the physical address of a configuration data structure.

|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description

| [31:0] | MCONFIGPTR | 0x00000000 | ROCST | 0x0 | MXLEN-bit read-only register that holds the physical address of a configuration data structure. 
|===

