!Feature
next_elt_id: 4
name: RV32M Division Operations
id: 7
display_order: 7
subfeatures: !!omap
- 000_DIV: !Subfeature
    name: 000_DIV
    tag: VP_IP007_P000
    next_elt_id: 4
    display_order: 0
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32_F007_S000_I000
        description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
          \ using signed arithmetic; rounding towards zero"
        reqt_doc: "Unprivileged ISA\nChapter 7.2"
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
          All possible rs2 registers are used.\nAll possible rd registers are used.\n\
          All possible register combinations where rs1 == rd are used\nAll possible\
          \ register combinations where rs2 == rd are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_div_cg.cp_rs1\nisacov.rv32m_div_cg.cp_rs2\nisacov.rv32m_div_cg.cp_rd\n\
          isacov.rv32m_div_cg.cp_rd_rs1_hazard\nisacov.rv32m_div_cg.cp_rd_rs2_hazard"
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32_F007_S000_I001
        description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
          \ using signed arithmetic; rounding towards zero"
        reqt_doc: "Unprivileged ISA\nChapter 7.2"
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
          \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
          \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\
          isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\
          \ \nisacov.rv32m_div_cg.cp_rs2_toggle"
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32_F007_S000_I002
        description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
          \ using signed arithmetic; rounding towards zero"
        reqt_doc: "Unprivileged ISA\nChapter 7.2"
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
          \ rd are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\
          isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\
          \ \nisacov.rv32m_div_cg.cp_rs2_toggle"
        comments: ''
    - '003': !VerifItem
        name: '003'
        tag: VP_ISA_RV32_F007_S000_I003
        description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\
          \ using signed arithmetic; rounding towards zero"
        reqt_doc: "Unprivileged ISA\nChapter 7.2"
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\
          \ rd = -2^31).\nExercise division by zero (returns -1 ; all bits set)"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_div_results_cg.cp_div_special_results\nisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow"
        comments: ''
- 001_REM: !Subfeature
    name: 001_REM
    tag: VP_IP007_P001
    next_elt_id: 4
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32_F007_S001_I000
        description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using signed arithmetic; remainder from the same division than DIV (the\
          \ sign of rd equals the sign of rs1)"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
          All possible rs2 registers are used.\nAll possible rd registers are used.\n\
          All possible register combinations where rs1 == rd are used\nAll possible\
          \ register combinations where rs2 == rd are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_rem_cg.cp_rs1\nisacov.rv32m_rem_cg.cp_rs2\nisacov.rv32m_rem_cg.cp_rd\n\
          isacov.rv32m_rem_cg.cp_rd_rs1_hazard\nisacov.rv32m_rem_cg.cp_rd_rs2_hazard"
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32_F007_S001_I001
        description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using signed arithmetic; remainder from the same division than DIV (the\
          \ sign of rd equals the sign of rs1)"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\
          \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\
          \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_rem_cg.cp_rs1_value\nisacov.rv32m_rem_cg.cp_rs2_value\n\
          isacov.rv32m_rem_cg.cross_rs1_rs2_value\nisacov.rv32m_rem_cg.cp_rs1_toggle\
          \ \nisacov.rv32m_rem_cg.cp_rs2_toggle"
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32_F007_S001_I002
        description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using signed arithmetic; remainder from the same division than DIV (the\
          \ sign of rd equals the sign of rs1)"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\
          \ rd are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_rem_cg.cp_rd_value\nisacov.rv32m_rem_cg.cp_rd_toggle"
        comments: ''
    - '003': !VerifItem
        name: '003'
        tag: VP_ISA_RV32_F007_S001_I003
        description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using signed arithmetic; remainder from the same division than DIV (the\
          \ sign of rd equals the sign of rs1)"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\
          \ rd = 0).\nExercise division by zero (returns rs1)"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_rem_results_cg.cp_div_zero\nisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow"
        comments: ''
- 002_DIVU: !Subfeature
    name: 002_DIVU
    tag: VP_IP007_P002
    next_elt_id: 4
    display_order: 2
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32_F007_S002_I000
        description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; rounding towards zero"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
          All possible rs2 registers are used.\nAll possible rd registers are used.\n\
          All possible register combinations where rs1 == rd are used\nAll possible\
          \ register combinations where rs2 == rd are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_divu_cg.cp_rs1\nisacov.rv32m_divu_cg.cp_rs2\n\
          isacov.rv32m_divu_cg.cp_rd\nisacov.rv32m_divu_cg.cp_rd_rs1_hazard\nisacov.rv32m_divu_cg.cp_rd_rs2_hazard"
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32_F007_S002_I001
        description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; rounding towards zero"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
          \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\
          \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_divu_cg.cp_rs1_value\nisacov.rv32m_divu_cg.cp_rs2_value\n\
          isacov.rv32m_divu_cg.cross_rs1_rs2_value\nisacov.rv32m_divu_cg.cp_rs1_toggle\
          \ \nisacov.rv32m_divu_cg.cp_rs2_toggle"
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32_F007_S002_I002
        description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; rounding towards zero"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\
          \ rd are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_divu_cg.cp_rd_value\nisacov.rv32m_divu_cg.cp_rd_toggle"
        comments: ''
    - '003': !VerifItem
        name: '003'
        tag: VP_ISA_RV32_F007_S002_I003
        description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; rounding towards zero"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: Exercise division by zero (returns 2^32-1 ; all bits set)
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: isacov.rv32m_divu_results_cg.cp_div_zero
        comments: ''
- 003_REMU: !Subfeature
    name: 003_REMU
    tag: VP_IP007_P003
    next_elt_id: 4
    display_order: 3
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32_F007_S003_I000
        description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; remainder from the same division than DIVU"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\
          All possible rs2 registers are used.\nAll possible rd registers are used.\n\
          All possible register combinations where rs1 == rd are used\nAll possible\
          \ register combinations where rs2 == rd are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_remu_cg.cp_rs1\nisacov.rv32m_remu_cg.cp_rs2\n\
          isacov.rv32m_remu_cg.cp_rd\nisacov.rv32m_remu_cg.cp_rd_rs1_hazard\nisacov.rv32m_remu_cg.cp_rd_rs2_hazard"
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32_F007_S003_I001
        description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; remainder from the same division than DIVU"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\
          \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\
          \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_remu_cg.cp_rs1_value\nisacov.rv32m_remu_cg.cp_rs2_value\n\
          isacov.rv32m_remu_cg.cross_rs1_rs2_value\nisacov.rv32m_remu_cg.cp_rs1_toggle\
          \ \nisacov.rv32m_remu_cg.cp_rs2_toggle"
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32_F007_S003_I002
        description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; remainder from the same division than DIVU"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\
          \ rd are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: "isacov.rv32m_remu_cg.cp_rd_value\nisacov.rv32m_remu_cg.cp_rd_toggle"
        comments: ''
    - '003': !VerifItem
        name: '003'
        tag: VP_ISA_RV32_F007_S003_I003
        description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\
          \ using unsigned arithmetic; remainder from the same division than DIVU"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: Exercise division by zero (returns rs1)
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: isacov.rv32m_remu_results_cg.cp_div_zero
        comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
