OpenHW
cva6
CV32A6_CSR
Apache_2.0_with_SHL_2.1
Other
32
Other
address_block
'h0
'h4000
32
register
mstatus
Machine Status
The ``mstatus`` register keeps track of and controls the hart’s current operating state.
'h300
32
true
read-write
SD
State Dirty
The SD bit is a read-only bit.``Legal Values``:0.
31
0x0
0x1
1
true
read-only
Not_Dirty
None of FS, VS or XS is dirty.
0
Dirty
Either FS, VS or XS is dirty.
1
WARL
reserved_0
Reserved
Reserved
23
0x0
0x1
8
read-write
WPRI
TSR
Trap SRET
The TSR bit supports intercepting the supervisor exception return instruction, SRET.
22
0x0
0x1
1
read-write
Permitted
Executing SRET in S-mode is permitted.
0
Not_Permitted
Illegal instruction exception raised by executing SRET in S-mode.
1
WARL
TW
Timeout Wait
The TW bit supports intercepting the WFI instruction.
21
0x0
0x1
1
read-write
Permitted
WFI may execute in lower privilege modes.
0
Not_Permitted
Illegal instruction exception raised by executing WFI in lower privilege mode that does not complete in bounded time limit.
1
WARL
TVM
Trap Virtual Memory
The TVM bit supports intercepting supervisor virtual-memory management operations.
20
0x0
0x1
1
read-write
Permitted
Reading or writing SATP and executing SFENCE.VMA are permitted in S-mode.
0
Not_Permitted
Illegal instruction exception is raised by reading or writing SATP or executing in S-mode SFENCE.VMA .
1
WARL
MXR
Make eXecutable Readable
The MXR bit modifies the privilege with which loads access virtual memory.
19
0x0
0x1
1
read-write
Not_Executable
Only loads from pages marked readable will succeed.
0
Executable
Loads from pages marked either readable or executable will succeed.
1
SUM
Supervisor User Memory
The SUM bit modifies the privilege with which S-mode loads and stores access virtual memory.
18
0x0
0x1
1
read-write
Not_Permitted
No access to U-mode pages with S-mode.
0
Permitted
Access to U-mode pages with S-mode is granted.
1
MPRV
Modify Privilege
The MPRV bit modifies the privilege mode at which loads and stores execute.
17
0x0
0x1
1
read-write
Normal
Loads and stores behave as normal.
0
Protected
Load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP.
1
XS
Extension State
The XS field encodes the status of the additional user-mode extensions and associated state.``Legal Values``:0.
15
0x0
0x3
2
true
read-only
Off
All off
0
Initial
None dirty or clean, some on
1
Clean
None dirty, some clean
2
Dirty
Some dirty
3
WARL
FS
Floating-point unit State
FS extension is not supported.``Legal Values``:0.
13
0x0
0x3
2
read-only
Off
0
Initial
1
Clean
2
Dirty
3
WARL
MPP
Machine mode Prior Privilege
Holds the previous privilege mode for machine mode.
11
0x0
0x3
2
read-write
U-mode
0
S-mode
1
Reserved
2
M-mode
3
VS
Vector extension State
V extension is not supported.``Legal Values``:0.
9
0x0
0x3
2
read-only
WARL
SPP
Supervisor mode Prior Privilege
Holds the previous privilege mode for supervisor mode.
8
0x0
0x1
1
read-write
U-mode
0
Otherwise
1
MPIE
Machine mode Prior Interrupt Enable
Indicates whether machine interrupts were enabled prior to trapping into machine mode.
7
0x0
0x1
1
read-write
Disabled
Interrupts were not enabled in M-mode.
0
Enabled
Interrupts were enabled in M-mode.
1
UBE
User mode Bit Endianess
UBE controls whether explicit load and store memory accesses made from U-mode are little-endian or big-endian.``Legal Values``:0.
6
0x0
0x1
1
read-write
Little-endian
0
Big-endian
1
WARL
SPIE
Supervisor mode Prior Interrupt Enable
Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.
5
0x0
0x1
1
read-write
Disabled
Interrupts were not enabled in S-mode.
0
Enabled
Interrupts were enabled in S-mode.
1
reserved_1
Reserved
Reserved
4
0x0
0x1
1
read-write
WPRI
MIE
Machine mode Interrupt Enable
Global interrupt-enable bit for Machine mode.
3
0x0
0x1
1
read-write
Disabled
Interrupts are disabled.
0
Enabled
Interrupts are enabled.
1
reserved_2
Reserved
Reserved
2
0x0
0x1
1
read-write
WPRI
SIE
Supervisor mode Interrupt Enable
Global interrupt-enable bit for Supervisor mode.
1
0x0
0x1
1
read-write
Disabled
Interrupts are disabled.
0
Enabled
Interrupts are enabled.
1
reserved_3
Reserved
Reserved
0
0x0
0x1
1
read-write
WPRI
M
misa
Machine ISA
The misa CSR is reporting the ISA supported by the hart.
'h301
32
read-write
MXL
Machine XLEN
The MXL field encodes the native base integer ISA width.``Legal Values``:1.
30
0x0
0x3
2
read-write
XLEN_32
1
XLEN_64
2
XLEN_128
3
WARL
Reserved_26
Reserved
Reserved.``Legal Values:``0.
26
0x0
0x1
4
read-write
WARL
Extensions
Extensions
The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet.``Legal Values``:0x141104.
0
0x141104
0x3ffffff
26
read-write
A
Atomic extension.
1
B
*Tentatively reserved for Bit-Manipulation extension.*
2
C
Compressed extension.
4
D
Double-precision floating-point extension.
8
E
RV32E base ISA.
16
F
Single-precision floating-point extension.
32
G
*Reserved.*
64
H
Hypervisor extension.
128
I
RV32I/64I/128I base ISA.
256
J
*Tentatively reserved for Dynamically Translated Languages extension.*
512
K
*Reserved.*
1024
L
*Reserved.*
2048
M
Integer Multiply/Divide extension.
4096
N
*Tentatively reserved for User-Level Interrupts extension.*
8192
O
*Reserved.*
16384
P
*Tentatively reserved for Packed-SIMD extension.*
32768
Q
Quad-precision floating-point extension.
65536
R
*Reserved.*
131072
S
Supervisor mode implemented.
262144
T
*Reserved.*
524288
U
User mode implemented.
1048576
V
*Tentatively reserved for Vector extension.*
2097152
W
*Reserved.*
4194304
X
Non-standard extensions present.
8388608
Y
*Reserved.*
16777216
Z
*Reserved.*
33554432
WARL
M
mie
Machine Interrupt Enable
This register contains machine interrupt enable bits.
'h304
32
read-write
Reserved_12
Reserved
Reserved.``Legal Values:``0.
12
0x0
0x1
4
read-write
WARL
MEIE
M-mode External Interrupt Enable
Enables machine mode external interrupts.
11
0x0
0x1
1
read-write
WARL
Reserved_10
Reserved
Reserved.``Legal Values:``0.
10
0x0
0x1
1
read-write
WARL
SEIE
S-mode External Interrupt Enable
Enables supervisor mode external interrupts.
9
0x0
0x1
1
read-write
WARL
UEIE
enables U-mode external interrupts.``Legal Values:``0.
8
0x0
0x1
1
read-write
WARL
MTIE
M-mode Timer Interrupt Enable
Enables machine mode timer interrupts.
7
0x0
0x1
1
read-write
WARL
Reserved_6
Reserved
Reserved.``Legal Values:``0.
6
0x0
0x1
1
read-write
WARL
STIE
S-mode Timer Interrupt Enable
Enables supervisor mode timer interrupts.
5
0x0
0x1
1
read-write
WARL
UTIE
timer interrupt-enable bit for U-mode.``Legal Values:``0.
4
0x0
0x1
1
read-write
WARL
MSIE
M-mode Software Interrupt Enable
Enables machine mode software interrupts.
3
0x0
0x1
1
read-write
Reserved_2
Reserved
Reserved.``Legal Values:``0.
2
0x0
0x1
1
read-write
WARL
SSIE
S-mode Software Interrupt Enable
Enables supervisor mode software interrupts.
1
0x0
0x1
1
read-write
WARL
USIE
enable U-mode software interrrupts.``Legal Values:``0.
0
0x0
0x1
1
read-write
WARL
M
mtvec
Machine Trap Vector
This register holds trap vector configuration, consisting of a vector base address and a vector mode.
'h305
32
read-write
BASE
The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.
2
0x0
0x3fffffff
30
read-write
WARL
MODE
Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0,1.
0
0x0
0x3
2
read-write
Direct
All exceptions set ``pc`` to BASE.
0
Vectored
Asynchronous interrupts set ``pc`` to BASE+4×cause.
1
Reserved_2
*Reserved.*
2
Reserved_3
*Reserved.*
3
WARL
M
mstatush
Upper 32-bits of Machine Status
The ``mstatush`` is the upper 32-bits of Machine status only for RV32.
'h310
32
true
read-write
reserved_0
Reserved
Reserved
0
0x0
0x1
4
read-write
WPRI
SBE
Supervisor mode Bit Endianess
SBE controls whether explicit load and store memory accesses made from S-mode are little-endian or big-endian.``Legal Values``:0.
4
0x0
0x1
1
read-write
Little-endian
0
Big-endian
1
WARL
MBE
Machine mode Bit Endianess
MBE controls whether explicit load and store memory accesses made from M-mode are little-endian or big-endian.``Legal Values``:0.
5
0x0
0x1
1
read-write
Little-endian
0
Big-endian
1
WARL
reserved_1
Reserved
Reserved
6
0x0
0x1
26
read-write
WPRI
M
mhpmevent3
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h323
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent4
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h324
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent5
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h325
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent6
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h326
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent7
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h327
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent8
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h328
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent9
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h329
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent10
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h32a
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent11
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h32b
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent12
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h32c
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent13
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h32d
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent14
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h32e
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent15
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h32f
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent16
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h330
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent17
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h331
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent18
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h332
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent19
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h333
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent20
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h334
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent21
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h335
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent22
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h336
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent23
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h337
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent24
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h338
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent25
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h339
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent26
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h33a
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent27
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h33b
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent28
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h33c
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent29
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h33d
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent30
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h33e
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mhpmevent31
Machine Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h33f
32
read-write
mhpmevent
Event selector CSRs.``Legal Values``:0.
0
0x0
0xffffffff
32
WARL
M
mscratch
Machine Scratch
This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception.
'h340
32
read-write
mscratch
Machine Scratch
Holds a value dedicated to Machine mode.
0
0x0
0xffffffff
32
read-write
M
mepc
Machine Exception Program Counter
This register must be able to hold all valid virtual addresses.
'h341
32
read-write
mepc
Machine Exception Program Counter
When a trap is taken into M-mode, ``mepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception.
0
0x0
0xffffffff
32
read-write
WARL
M
mcause
Machine Cause
When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. Machine cause register (``mcause``) values after trap are shown in the following table. ========= ============== ============================== Interrupt Exception Code Description ========= ============== ============================== 1 0 *Reserved* 1 1 Supervisor software interrupt 1 2-4 *Reserved* 1 5 Supervisor timer interrupt 1 6-8 *Reserved* 1 9 Supervisor external interrupt 1 10-15 *Reserved* 1 ≥16 *Designated for platform use* 0 0 Instruction address misaligned 0 1 Instruction access fault 0 2 Illegal instruction 0 3 Breakpoint 0 4 Load address misaligned 0 5 Load access fault 0 6 Store/AMO address misaligned 0 7 Store/AMO access fault 0 8 Environment call from U-mode 0 9 Environment call from S-mode 0 10-11 *Reserved* 0 12 Instruction page fault 0 13 Load page fault 0 14 *Reserved* 0 15 Store/AMO page fault 0 16-23 *Reserved* 0 24-31 *Designated for custom use* 0 32-47 *Reserved* 0 48-63 *Designated for custom use* 0 ≥64 *Reserved* ========= ============== ==============================
'h342
32
read-write
Interrupt
Interrupt
This bit is set if the trap was caused by an interrupt.
31
0x0
0x1
1
read-write
exception_code
Exception Code
This field contains a code identifying the last exception or interrupt.
0
0x0
0x7fffffff
31
read-write
WLRL
M
mtval
Machine Trap Value
When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap.
'h343
32
read-write
mtval
Machine Trap Value
If ``mtval`` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address. If ``mtval`` is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then ``mtval`` will contain the virtual address of the portion of the access that caused the fault. If ``mtval`` is written with a nonzero value when an instruction access-fault or page-fault exception occurs on a system with variable-length instructions, then ``mtval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``mepc`` will point to the beginning of the instruction.
0
0x0
0xffffffff
32
read-write
WARL
M
mip
Machine Interrupt Pending
This register contains machine interrupt pending bits.
'h344
32
true
read-write
Reserved_12
Reserved
Reserved.``Legal Values:``0.
12
0x0
0x1
4
read-write
WARL
MEIP
M-mode External Interrupt Pending
The interrupt-pending bit for machine-level external interrupts.
11
0x0
0x1
1
true
read-only
Reserved_10
Reserved
Reserved.``Legal Values:``0.
10
0x0
0x1
1
read-write
WARL
SEIP
S-mode External Interrupt Pending
The interrupt-pending bit for supervisor-level external interrupts.
9
0x0
0x1
1
read-write
UEIP
enables external interrupts.``Legal Values:``0.
8
0x0
0x1
1
read-write
MTIP
M-mode Timer Interrupt Pending
The interrupt-pending bit for machine-level timer interrupts.
7
0x0
0x1
1
true
read-only
Reserved_6
Reserved
Reserved.``Legal Values:``0.
6
0x0
0x1
1
read-write
WARL
STIP
S-mode Timer Interrupt Pending
The interrupt-pending bit for supervisor-level timer interrupts.
5
0x0
0x1
1
read-write
UTIP
Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0.
4
0x0
0x1
1
read-write
MSIP
M-mode Software Interrupt Pending
The interrupt-pending bit for machine-level software interrupts.
3
0x0
0x1
1
true
read-only
Reserved_2
Reserved
Reserved.``Legal Values:``0.
2
0x0
0x1
1
read-write
WARL
SSIP
S-mode Software Interrupt Pending
The interrupt-pending bit for supervisor-level software interrupts.
1
0x0
0x1
1
read-write
USIP
A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0.
0
0x0
0x1
1
read-write
M
pmpcfg0
Physical Memory Protection Config 0
Holds configuration 0-3.
'h3a0
32
read-write
pmp3cfg
Physical Memory Protection 3 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp2cfg
Physical Memory Protection 2 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp1cfg
Physical Memory Protection 1 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp0cfg
Physical Memory Protection 0 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpcfg1
Physical Memory Protection Config 1
Holds configuration 4-7.
'h3a1
32
read-write
pmp7cfg
Physical Memory Protection 7 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp6cfg
Physical Memory Protection 6 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp5cfg
Physical Memory Protection 5 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp4cfg
Physical Memory Protection 4 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpcfg2
Physical Memory Protection Config 2
Holds configuration 8-11.
'h3a2
32
read-write
pmp11cfg
Physical Memory Protection 11 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp10cfg
Physical Memory Protection 10 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp9cfg
Physical Memory Protection 9 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp8cfg
Physical Memory Protection 8 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpcfg3
Physical Memory Protection Config 3
Holds configuration 12-15.
'h3a3
32
read-write
pmp15cfg
Physical Memory Protection 15 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp14cfg
Physical Memory Protection 14 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp13cfg
Physical Memory Protection 13 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp12cfg
Physical Memory Protection 12 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpaddr0
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b0
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr1
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b1
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr2
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b2
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr3
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b3
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr4
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b4
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr5
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b5
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr6
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b6
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr7
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b7
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr8
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b8
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr9
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3b9
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr10
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3ba
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr11
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3bb
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr12
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3bc
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr13
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3bd
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr14
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3be
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
pmpaddr15
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3bf
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
icache
Instruction Cache
Custom Register to enable/disable for Icache [bit 0]
'h7C0
32
read-write
reserved_0
Reserved
Reserved
1
0x0
0x1
31
read-only
icache
Instruction Cache
Custom Register
0
0x1
0x1
1
read-write
M
mcycle
M-mode Cycle counter
Counts the number of clock cycles executed by the processor core on which the hart is running.
'hB00
32
read-write
count
Count
Counts the number of clock cycles executed by the processor core.
0
0x0
0xffffffff
32
read-write
M
minstret
Machine Instruction Retired counter
Counts the number of instructions the hart has retired.
'hB02
32
read-write
count
Count
Counts the number of instructions the hart has retired.
0
0x0
0xffffffff
32
read-write
M
mcycleh
Upper 32-bits of M-mode Cycle counter
Counts the number of clock cycles executed by the processor core on which the hart is running.
'hB80
32
read-write
count
Count
Counts the number of clock cycles executed by the processor core.
0
0x0
0xffffffff
32
read-write
M
minstreth
Upper 32-bits of Machine Instruction Retired counter
Counts the number of instructions the hart has retired.
'hB82
32
read-write
count
Count
Counts the number of instructions the hart has retired.
0
0x0
0xffffffff
32
read-write
M
mhpmcounter3
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb03
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter4
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb04
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter5
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb05
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter6
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb06
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter7
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb07
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter8
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb08
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter9
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb09
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter10
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb0a
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter11
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb0b
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter12
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb0c
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter13
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb0d
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter14
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb0e
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter15
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb0f
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter16
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb10
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter17
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb11
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter18
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb12
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter19
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb13
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter20
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb14
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter21
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb15
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter22
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb16
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter23
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb17
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter24
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb18
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter25
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb19
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter26
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb1a
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter27
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb1b
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter28
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb1c
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter29
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb1d
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter30
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb1e
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounter31
Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hb1f
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh3
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb83
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh4
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb84
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh5
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb85
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh6
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb86
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh7
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb87
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh8
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb88
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh9
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb89
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh10
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb8a
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh11
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb8b
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh12
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb8c
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh13
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb8d
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh14
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb8e
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh15
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb8f
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh16
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb90
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh17
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb91
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh18
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb92
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh19
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb93
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh20
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb94
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh21
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb95
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh22
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb96
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh23
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb97
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh24
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb98
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh25
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb99
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh26
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb9a
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh27
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb9b
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh28
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb9c
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh29
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb9d
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh30
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb9e
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
mhpmcounterh31
Upper 32 bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter only for RV32.
6
'hb9f
32
read-write
count
Count
``Legal Values``: 0.
0
0x0
0xffffffff
32
WARL
M
cycle
Cycle counter
Cycle counter for RDCYCLE instruction. Shadow of mcycle.
'hC00
32
true
read-only
count
Count
Count
0
0x0
0xffffffff
32
true
read-only
U
instret
Instruction Retired counter
Instructions-retired counter for RDINSTRET instruction. Shadow of minstret.
'hC02
32
true
read-only
count
Count
Count
0
0x0
0xffffffff
32
true
read-only
U
cycleh
Upper 32-bits of Cycle counter
Cycle counter for RDCYCLE instruction. Shadow of mcycleh.
'hC80
32
true
read-only
count
Count
Count
0
0x0
0xffffffff
32
true
read-only
U
instreth
Upper 32-bits of Instruction Retired counter
Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth.
'hC82
32
true
read-only
count
Count
Count
0
0x0
0xffffffff
32
true
read-only
U
mvendorid
Machine Vendor ID
This register provids the JEDEC manufacturer ID of the provider of the core.
'hF11
32
true
read-only
bank
Bank
Contain encoding for number of one-byte continuation codes discarding the parity bit.
7
0xC0
0x1ffffff
25
true
read-only
offset
Offset
Contain encording for the final byte discarding the parity bit.
0
0x20
0x7f
7
true
read-only
M
marchid
Machine Architecture ID
This register encodes the base microarchitecture of the hart.
'hF12
32
true
read-only
architecture_id
Architecture ID
Provide Encoding the base microarchitecture of the hart.
0
0x3
0xffffffff
32
true
read-only
M
mimpid
Machine Implementation ID
Provides a unique encoding of the version of the processor implementation.
'hF13
32
true
read-only
implementation
Implementation
Provides unique encoding of the version of the processor implementation.
0
0x0
0xffffffff
32
true
read-only
M
mhartid
Machine Hardware Thread ID
This register contains the integer ID of the hardware thread running the code.
'hF14
32
true
read-only
hart_id
Hart ID
Contains the integer ID of the hardware thread running the code.
0
0x0
0xffffffff
32
true
read-only
M
32