!Feature
next_elt_id: 3
name: Fetch stage
id: 10
display_order: 10
subfeatures: !!omap
- 001_MMU translation: !Subfeature
    name: 001_MMU translation
    tag: VP_IP010_P001
    next_elt_id: 2
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_FRONTEND_F010_S001_I000
        description: The Fetch stage asks the MMU to translate the requested address.
        reqt_doc: FRONTEND sub-system/functionality/Fetch stage
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: Execute a program with virtual PC
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 16
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_FRONTEND_F010_S001_I001
        description: The Fetch stage asks the MMU to translate the requested address.
        reqt_doc: FRONTEND sub-system/functionality/Fetch stage
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: Check the translation does not impact execution time by executing
          Coremark in pphysical and virtual modes.
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 16
        coverage_loc: ''
        comments: ''
- 002_Exceptions: !Subfeature
    name: 002_Exceptions
    tag: VP_IP010_P002
    next_elt_id: 4
    display_order: 2
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_FRONTEND_F010_S002_I000
        description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback
          potential exceptions generated by the memory fetch request. They can be
          bus errors, invalid accesses or instruction page faults.
        reqt_doc: FRONTEND sub-system/functionality/Fetch stage
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: 'Generate a bus error exception by UVM or by test (to be decided)
          and check that the exception address is fetched. Functional cov: a bus error
          exception occurs.'
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 8
        coverage_loc: ''
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_FRONTEND_F010_S002_I002
        description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback
          potential exceptions generated by the memory fetch request. They can be
          bus errors, invalid accesses or instruction page faults.
        reqt_doc: FRONTEND sub-system/functionality/Fetch stage
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: 'Generate an invalid access exception by UVM or by test (to be
          decided) and check that the exception address is fetched. Functional cov:
          an invalid access exception occurs.'
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 8
        coverage_loc: ''
        comments: ''
    - '003': !VerifItem
        name: '003'
        tag: VP_FRONTEND_F010_S002_I003
        description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback
          potential exceptions generated by the memory fetch request. They can be
          bus errors, invalid accesses or instruction page faults.
        reqt_doc: FRONTEND sub-system/functionality/Fetch stage
        ref_mode: ''
        ref_page: ''
        ref_section: ''
        ref_viewer: ''
        verif_goals: Generate an instruction page faults and check that the exception
          is triggered
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 16
        coverage_loc: ''
        comments: ''
vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
