!Feature
next_elt_id: 3
name: RV32Zba Address generation instructions
id: 19
display_order: 19
subfeatures: !!omap
- 000_SH1ADD: !Subfeature
    name: 000_SH1ADD
    tag: VP_ISA_RV32_F019_S000
    next_elt_id: 3
    display_order: 0
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32_F019_S000_I000
        description: "sh1add rd, rs1, rs2\nx[rd] = (x[rs1] << 1) + x[rs2]\nShift the
          value in rs1 by 1 bit, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n
          All possible rs2 registers are used.\nAll possible rd registers are used.\n
          All possible register combinations where rs1 == rd are used\nAll possible
          register combinations where rs2 == rd are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32_F019_S000_I001
        description: "sh1add rd, rs1, rs2\nx[rd] = (x[rs1] << 1) + x[rs2]\nShift the
          value in rs1 by 1 bit, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value
          is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero
          values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32_F019_S000_I002
        description: "sh1add rd, rs1, rs2\nx[rd] = (x[rs1] << 1) + x[rs2]\nShift the
          value in rs1 by 1 bit, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of
          rd are toggled"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
- 001_SH2ADD: !Subfeature
    name: 001_SH2ADD
    tag: VP_ISA_RV32_F019_S001
    next_elt_id: 3
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32_F019_S001_I000
        description: "sh2add rd, rs1, rs2\nx[rd] = (x[rs1] << 2) + x[rs2]\nShift the
          value in rs1 by 2 bits, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n
          All possible rs2 registers are used.\nAll possible rd registers are used.\n
          All possible register combinations where rs1 == rd are used\nAll possible
          register combinations where rs2 == rd are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32_F019_S001_I001
        description: "sh2add rd, rs1, rs2\nx[rd] = (x[rs1] << 2) + x[rs2]\nShift the
          value in rs1 by 2 bits, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value
          is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero
          values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32_F019_S001_I002
        description: "sh2add rd, rs1, rs2\nx[rd] = (x[rs1] << 2) + x[rs2]\nShift the
          value in rs1 by 2 bits, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of
          rd are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
- 002_SH3ADD: !Subfeature
    name: 002_SH3ADD
    tag: VP_ISA_RV32_F019_S002
    next_elt_id: 3
    display_order: 2
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32_F019_S002_I000
        description: "sh3add rd, rs1, rs2\nx[rd] = (x[rs1] << 3) + x[rs2]\nShift the
          value in rs1 by 3 bits, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n
          All possible rs2 registers are used.\nAll possible rd registers are used.\n
          All possible register combinations where rs1 == rd are used\nAll possible
          register combinations where rs2 == rd are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32_F019_S002_I001
        description: "sh3add rd, rs1, rs2\nx[rd] = (x[rs1] << 3) + x[rs2]\nShift the
          value in rs1 by 3 bits, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value
          is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero
          values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32_F019_S002_I002
        description: "sh3add rd, rs1, rs2\nx[rd] = (x[rs1] << 3) + x[rs2]\nShift the
          value in rs1 by 3 bits, add to it rs2 and store the result in rd."
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of
          rd are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
