!Feature
next_elt_id: 2
name: CVA6 CSRs counters functionality checking
id: 2
display_order: 2
subfeatures: !!omap
- 000_Counter value: !Subfeature
    name: 000_Counter value
    tag: VP_csr-embedded-access_F002_S000
    next_elt_id: 2
    display_order: 0
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_csr-embedded-access_F002_S000_I000
        description: Check that counter registers cycle/mcycle and cycleh/mcycleh
          increment at each clock.
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: Performing two continuous reads to the same register and ensure
          that the value of the second read from counter CSR is greater than the value
          of the initial read.
        pfc: 1
        test_type: 1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: In a RISC-V 32bits architecture cycle/mcycle and cycleh/mcycleh
          holds low 32 bits and high 32 bits respectively of the count of clock cycles
          executed by the processor.
    - '001': !VerifItem
        name: '001'
        tag: VP_csr-embedded-access_F002_S000_I001
        description: Check that counter registers instret/instreth and minstret/minstreth
          increment after each instruction and values match reference model.
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: Performing two continuous reads to the same register and ensure
          that the value of the second read from counter CSR is greater than the value
          of the initial read.
        pfc: 3
        test_type: 1
        cov_method: 0
        cores: 56
        coverage_loc: ''
        comments: In a RISC-V 32bits architecture instret/minstret and instreth/minstreth
          holds low 32 bits and high 32 bits respectively of the count of executed
          instructions by the processor.
- 001_Counter overflow: !Subfeature
    name: 001_Counter overflow
    tag: VP_csr-embedded-access_F002_S001
    next_elt_id: 2
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_csr-embedded-access_F002_S001_I000
        description: "Check the behaviour of counter CSRs cycle, cycleh, mcycle, mcycleh
          when reaching maximum value.\ncycle and mcycle should be 0 after reaching
          maximum value and cycleh/mcycleh should increment by 1. cycleh/mcycleh should
          be set to 0 after reaching maximum value."
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "1- Write mcycle/mcycleh to higher or maximum 32bit value.\n
          2- Perform some random read/write CSR registers.\n3- Ensure that counters
          reset to 0."
        pfc: 1
        test_type: 1
        cov_method: 0
        cores: 56
        coverage_loc: ''
        comments: 'Related counter registers: cycle, cycleh, mcycle, mcycleh.'
    - '001': !VerifItem
        name: '001'
        tag: VP_csr-embedded-access_F002_S001_I001
        description: "Check the behaviour of counter CSRs instret, instreth, minstret,
          minstreth when reaching maximum value which should match reference model.
          \ninstret and minstret should be 0 after reaching maximum value and instreth/minstreth
          should increment by 1. instreth/minstreth should be set to 0 after reaching
          maximum value."
        reqt_doc: 
          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "1- Write minstret/minstreth to higher or maximum 32bit value.\n
          2- Perform some random read/write CSR registers.\n3- Ensure that counters
          reset to 0."
        pfc: 3
        test_type: 1
        cov_method: 0
        cores: 56
        coverage_loc: ''
        comments: 'Related counter registers: instret, instreth, minstret, minstreth.'
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
