OpenHW
cva6
CV32A6_CSR
CV32A60X
Other
32
Other
address_block
'h0
'h4000
32
register
fflags
Floating-Point Accrued Exceptions
The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``.
'h1
32
read-write
NV
Invalid Operation
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
4
0x0
0x1
1
read-write
DZ
Divide by Zero
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
3
0x0
0x1
1
read-write
OF
Overflow
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
2
0x0
0x1
1
read-write
UF
Underflow
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
1
0x0
0x1
1
read-write
NX
Inexact
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
0
0x0
0x1
1
read-write
U
frm
Floating-Point Dynamic Rounding Mode
The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``.
'h2
32
read-write
FRM
Floating-Point Rounding Mode
Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in ``frm``. Rounding modes are encoded as shown in the enumerated value. A value of 111 in the instruction’s *rm* field selects the dynamic rounding mode held in ``frm``. If ``frm`` is set to an invalid value (101–111), any subsequent attempt to execute a floating-point operation with a dynamic rounding mode will raise an illegal instruction exception. Some instructions, including widening conversions, have the *rm* field but are nevertheless unaffected by the rounding mode; software should set their *rm* field to RNE (000).
0
0x0
0x7
3
read-write
RNE
Round to Nearest, ties to Even
0
RTZ
Round towards Zero
1
RDN
Round Down
2
RUP
Round Up
3
RMM
Round to Nearest, ties to Max Magnitude
4
INVALID_5
*Reserved for future use.*
5
INVALID_6
*Reserved for future use.*
6
DYN
In instruction’s *rm* field, selects dynamic rounding mode; In Rounding Mode register, *Invalid*.
7
U
fcsr
Floating-Point Control and Status Register
The floating-point control and status register, ``fcsr``, is a RISC-V control and status register (CSR). It is a read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags.

The ``fcsr`` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads ``fcsr`` by copying it into integer register *rd*. FSCSR swaps the value in ``fcsr`` by copying the original value into integer register *rd*, and then writing a new value obtained from integer register *rs1* into ``fcsr``.

The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``.
'h3
32
read-write
FRM
Floating-Point Rounding Mode
Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in ``frm``. Rounding modes are encoded as shown in the enumerated value. A value of 111 in the instruction’s *rm* field selects the dynamic rounding mode held in ``frm``. If ``frm`` is set to an invalid value (101–111), any subsequent attempt to execute a floating-point operation with a dynamic rounding mode will raise an illegal instruction exception. Some instructions, including widening conversions, have the *rm* field but are nevertheless unaffected by the rounding mode; software should set their *rm* field to RNE (000).
5
0x0
0x7
3
read-write
RNE
Round to Nearest, ties to Even
0
RTZ
Round towards Zero
1
RDN
Round Down
2
RUP
Round Up
3
RMM
Round to Nearest, ties to Max Magnitude
4
INVALID_5
*Reserved for future use.*
5
INVALID_6
*Reserved for future use.*
6
DYN
In instruction’s *rm* field, selects dynamic rounding mode; In Rounding Mode register, *Invalid*.
7
NV
Invalid Operation
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
4
0x0
0x1
1
read-write
DZ
Divide by Zero
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
3
0x0
0x1
1
read-write
OF
Overflow
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
2
0x0
0x1
1
read-write
UF
Underflow
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
1
0x0
0x1
1
read-write
NX
Inexact
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
0
0x0
0x1
1
read-write
U
sstatus
Supervisor Status
The ``sstatus`` register keeps track of the processor’s current operating state.

The ``sstatus`` register is a subset of the ``mstatus`` register.
'h100
32
true
read-write
SD
State Dirty
The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory. If FS, XS, and VS are all read-only zero, then SD is also always zero.
31
0x0
0x1
1
true
read-only
MXR
Make eXecutable Readable
The MXR bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.
19
0x0
0x1
1
read-write
SUM
Supervisor User Memory
The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect. Note that, while SUM is ordinarily ignored when not executing in S-mode, it *is* in effect when MPRV=1 and MPP=S. SUM is read-only 0 if S-mode is not supported or if ``satp``.MODE is read-only 0.
18
0x0
0x1
1
read-write
XS
Extension State
The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user-mode extensions. The XS field encodes the status of the additional user-mode extensions and associated state.

This field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process.
15
0x0
0x3
2
true
read-only
Off
All off
0
Initial
None dirty or clean, some on
1
Clean
None dirty, some clean
2
Dirty
Some dirty
3
FS
Floating-point unit State
The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit. The FS field encodes the status of the floating-point unit state, including the floating-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``.

This field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process.
13
0x0
0x3
2
read-write
Off
0
Initial
1
Clean
2
Dirty
3
WARL
SPP
Supervisor mode Prior Privilege
SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise. When an SRET instruction is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0.
8
0x0
0x1
1
read-write
SPIE
Supervisor mode Prior Interrupt Enable
The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.
5
0x0
0x1
1
read-write
UPIE
When a URET instruction is executed, UIE is set to UPIE, and UPIE is set to 1.
4
0x0
0x1
1
read-write
SIE
Supervisor mode Interrupt Enable
The SIE bit enables or disables all interrupts in supervisor mode. When SIE is clear, interrupts are not taken while in supervisor mode. When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled. The supervisor can disable individual interrupt sources using the ``sie`` CSR.
1
0x0
0x1
1
read-write
UIE
The UIE bit enables or disables user-mode interrupts.
0
0x0
0x1
1
read-write
S
sie
Supervisor Interrupt Enable
The ``sie`` is the register containing supervisor interrupt enable bits.
'h104
32
read-write
Reserved_10
Reserved
Reserved.``Legal Values:``0.
10
0x0
0x1
5
read-write
WARL
SEIE
Supervisor-level External Interrupt Enable
SEIE is the interrupt-enable bit for supervisor-level external interrupts.
9
0x0
0x1
1
read-write
WARL
UEIE
User-level external interrupts are disabled when the UEIE bit in the sie register is clear.``Legal Values:``0.
8
0x0
0x1
1
read-write
WARL
Reserved_6
Reserved
Reserved.``Legal Values:``0.
6
0x0
0x1
2
read-write
WARL
STIE
Supervisor-level Timer Interrupt Enable
STIE is the interrupt-enable bit for supervisor-level timer interrupts.
5
0x0
0x1
1
read-write
WARL
UTIE
User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.``Legal Values:``0.
4
0x0
0x1
1
read-write
WARL
Reserved_2
Reserved
Reserved.``Legal Values:``0.
2
0x0
0x1
2
read-write
WARL
SSIE
Supervisor-level Software Interrupt Enable
SSIE is the interrupt-enable bit for supervisor-level software interrupts.
1
0x0
0x1
1
read-write
WARL
USIE
User-level software interrupts are disabled when the USIE bit in the sie register is clear.``Legal Values:``0.
0
0x0
0x1
1
read-write
WARL
S
stvec
Supervisor Trap Vector Base Address
The ``stvec`` register holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
'h105
32
read-write
BASE
The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.
2
0x0
0x3fffffff
30
read-write
WARL
MODE
When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number.``Legal Values :``0,1.
0
0x0
0x3
2
read-write
Direct
All exceptions set ``pc`` to BASE.
0
Vectored
Asynchronous interrupts set pc to BASE+4×cause.
1
Reserved_2
*Reserved*
2
Reserved_3
*Reserved*
3
WARL
S
scounteren
Supervisor Counter Enable
The counter-enable register ``scounteren`` controls the availability of the hardware performance monitoring counters to U-mode.
'h106
32
read-write
HPMn
Hpmcountern
When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
3
0x0
0x1fffffff
29
read-write
IR
Instret
When IR is clear, attempts to read the ``instret`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
2
0x0
0x1
1
read-write
TM
Time
When TM is clear, attempts to read the ``time`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
1
0x0
0x1
1
read-write
CY
Cycle
When CY is clear, attempts to read the ``cycle`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
0
0x0
0x1
1
read-write
S
sscratch
Supervisor Scratch
The ``sscratch`` register is dedicated for use by the supervisor.
'h140
32
read-write
SSCRATCH
Supervisor Scratch
Typically, ``sscratch`` is used to hold a pointer to the hart-local supervisor context while the hart is executing user code. At the beginning of a trap handler, ``sscratch`` is swapped with a user register to provide an initial working register.
0
0x0
0xffffffff
32
read-write
S
sepc
Supervisor Exception Program Counter
When a trap is taken into S-mode, ``sepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, ``sepc`` is never written by the implementation, though it may be explicitly written by software.
'h141
32
read-write
SEPC
Supervisor Exception Program Counter
The low bit of SEPC (SEPC[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (SEPC[1:0]) are always zero.
0
0x0
0xffffffff
32
read-write
WARL
S
scause
Supervisor Cause
When a trap is taken into S-mode, ``scause`` is written with a code indicating the event that caused the trap. Otherwise, ``scause`` is never written by the implementation, though it may be explicitly written by software.

Supervisor cause register (``scause``) values after trap are shown in the following table. ========= ============== ============================== Interrupt Exception Code Description ========= ============== ============================== 1 0 *Reserved* 1 1 Supervisor software interrupt 1 2-4 *Reserved* 1 5 Supervisor timer interrupt 1 6-8 *Reserved* 1 9 Supervisor external interrupt 1 10-15 *Reserved* 1 ≥16 *Designated for platform use* 0 0 Instruction address misaligned 0 1 Instruction access fault 0 2 Illegal instruction 0 3 Breakpoint 0 4 Load address misaligned 0 5 Load access fault 0 6 Store/AMO address misaligned 0 7 Store/AMO access fault 0 8 Environment call from U-mode 0 9 Environment call from S-mode 0 10-11 *Reserved* 0 12 Instruction page fault 0 13 Load page fault 0 14 *Reserved* 0 15 Store/AMO page fault 0 16-23 *Reserved* 0 24-31 *Designated for custom use* 0 32-47 *Reserved* 0 48-63 *Designated for custom use* 0 ≥64 *Reserved* ========= ============== ==============================
'h142
32
read-write
Interrupt
The Interrupt bit in the ``scause`` register is set if the trap was caused by an interrupt.
31
0x0
0x1
1
read-write
Exception_Code
Exception Code
The Exception Code field contains a code identifying the last exception or interrupt.
0
0x0
0x7fffffff
31
read-write
WLRL
S
stval
Supervisor Trap Value
When a trap is taken into S-mode, ``stval`` is written with exception-specific information to assist software in handling the trap. Otherwise, ``stval`` is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set ``stval`` informatively and which may unconditionally set it to zero.
'h143
32
read-write
STVAL
Supervisor Trap Value
If ``stval`` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then ``stval`` will contain the faulting virtual address.

If ``stval`` is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then ``stval`` will contain the virtual address of the portion of the access that caused the fault.

If ``stval`` is written with a nonzero value when an instruction access-fault or page-fault exception occurs on a system with variable-length instructions, then ``stval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``sepc`` will point to the beginning of the instruction.

The ``stval`` register can optionally also be used to return the faulting instruction bits on an illegal instruction exception (``sepc`` points to the faulting instruction in memory). If ``stval`` is written with a nonzero value when an illegal-instruction exception occurs, then ``stval`` will contain the shortest of:

* the actual faulting instruction * the first ILEN bits of the faulting instruction * the first SXLEN bits of the faulting instruction

The value loaded into ``stval`` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero. For other traps, ``stval`` is set to zero, but a future standard may redefine ``stval’s`` setting for other traps.
0
0x0
0xffffffff
32
read-write
WARL
S
sip
Supervisor Interrupt Pending
The ``sip`` register contains information on pending interrupts.
'h144
32
true
read-write
Reserved_10
Reserved
Reserved.``Legal Values:``0.
10
0x0
0x1
5
read-write
WARL
SEIP
Supervisor-level External Interrupt Pending
SEIP is the interrupt-pending bit for supervisor-level external interrupts.
9
0x0
0x1
1
true
read-only
WARL
UEIP
UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.``Legal Values:``0.
8
0x0
0x1
1
read-write
WARL
Reserved_6
Reserved
Reserved.``Legal Values:``0.
6
0x0
0x1
2
read-write
WARL
STIP
Supervisor-level Timer Interrupt Pending
SEIP is the interrupt-pending bit for supervisor-level timer interrupts.
5
0x0
0x1
1
true
read-only
WARL
UTIP
A user-level timer interrupt is pending if the UTIP bit in the sip register is set.``Legal Values:``0.
4
0x0
0x1
1
read-write
WARL
Reserved_2
Reserved
Reserved.``Legal Values:``0.
2
0x0
0x1
2
read-write
WARL
SSIP
Supervisor-level Software Interrupt Pending
SSIP is the interrupt-pending bit for supervisor-level software interrupts.
1
0x0
0x1
1
true
read-only
WARL
USIP
A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0.
0
0x0
0x1
1
read-write
WARL
S
satp
Supervisor Address Translation and Protection
The ``satp`` register controls supervisor-mode address translation and protection.

The ``satp`` register is considered active when the effective privilege mode is S-mode or U-mode. Executions of the address-translation algorithm may only begin using a given value of ``satp`` when ``satp`` is active.

.. note:: Writing ``satp`` does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches. If the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to execute an SFENCE.VMA instruction after, or in some cases before, writing ``satp``.
'h180
32
read-write
MODE
Mode
This bitfield selects the current address-translation scheme.

When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme.

To select MODE=Bare, software must write zero to the remaining fields of ``satp`` (bits 30–0). Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an ``unspecified`` effect on the value that the remaining fields assume and an ``unspecified`` effect on address translation and protection behavior.
31
0x0
0x1
1
read-write
Bare
No translation or protection.
0
Sv32
Page-based 32-bit virtual addressing.
1
WARL
ASID
Address Space Identifier
This bitfield facilitates address-translation fences on a per-address-space basis.
22
0x0
0x1ff
9
read-write
WARL
PPN
Physical Page Number
This bitfield holds the root page table, i.e., its supervisor physical address divided by 4 KiB.
0
0x0
0x3fffff
22
read-write
WARL
S
mstatus
Machine Status
The ``mstatus`` register keeps track of and controls the hart’s current operating state.
'h300
32
true
read-write
SD
State Dirty
The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory. If FS, XS, and VS are all read-only zero, then SD is also always zero.
31
0x0
0x1
1
true
read-only
WPRI3
Reserved Writes Preserve Values, Reads Ignore Value
Reserved Writes Preserve Values, Reads Ignore Value
23
0x0
0x1
8
read-write
WPRI
TSR
Trap SRET
The TSR bit supports intercepting the supervisor exception return instruction, SRET. When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction exception. When TSR=0, this operation is permitted in S-mode.
22
0x0
0x1
1
read-write
WARL
TW
Timeout Wait
The TW bit supports intercepting the WFI instruction. When TW=0, the WFI instruction may execute in lower privilege modes when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal instruction exception. The time limit may always be 0, in which case WFI always causes an illegal instruction exception in less-privileged modes when TW=1.
21
0x0
0x1
1
read-write
WARL
TVM
Trap Virtual Memory
The TVM bit supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the ``satp`` CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal instruction exception. When TVM=0, these operations are permitted in S-mode.
20
0x0
0x1
1
read-write
WARL
MXR
Make eXecutable Readable
The MXR bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.
19
0x0
0x1
1
read-write
SUM
Supervisor User Memory
The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect. Note that, while SUM is ordinarily ignored when not executing in S-mode, it is in effect when MPRV=1 and MPP=S.
18
0x0
0x1
1
read-write
MPRV
Modify Privilege
The MPRV (Modify PRiVilege) bit modifies the effective privilege mode, i.e., the privilege level at which loads and stores execute. When MPRV=0, loads and stores behave as normal, using the translation and protection mechanisms of the current privilege mode. When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP. Instruction address-translation and protection are unaffected by the setting of MPRV.
17
0x0
0x1
1
read-write
XS
Extension State
The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user-mode extensions. The XS field encodes the status of the additional user-mode extensions and associated state.

This field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process.
15
0x0
0x3
2
true
read-only
Off
All off
0
Initial
None dirty or clean, some on
1
Clean
None dirty, some clean
2
Dirty
Some dirty
3
FS
Floating-point unit State
The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit. The FS field encodes the status of the floating-point unit state, including the floating-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``.

This field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process.
13
0x0
0x3
2
read-write
Off
0
Initial
1
Clean
2
Dirty
3
WARL
MPP
Machine mode Prior Privilege
Holds the previous privilege mode for machine mode.
11
0x0
0x3
2
read-write
VS
Vector extension State
V extension is not supported VS=0.
9
0x0
0x3
2
read-only
WARL
SPP
Supervisor mode Prior Privilege
Holds the previous privilege mode for supervisor mode.
8
0x0
0x1
1
read-write
MPIE
Machine mode Prior Interrupt Enable
Indicates whether machine interrupts were enabled prior to trapping into machine mode.
7
0x0
0x1
1
read-write
UBE
User Breakpoint Enable
UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).
6
0x0
0x1
1
read-write
WARL
SPIE
Supervisor mode Prior Interrupt Enable
Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.
5
0x0
0x1
1
read-write
WPRI2
Reserved Writes Preserve Values, Reads Ignore Value
Reserved Writes Preserve Values, Reads Ignore Value
4
0x0
0x1
1
read-write
WPRI
MIE
Machine mode Interrupt Enable
Global interrupt-enable bit for Machine mode.
3
0x0
0x1
1
read-write
WPRI1
Reserved Writes Preserve Values, Reads Ignore Value
Reserved Writes Preserve Values, Reads Ignore Value
2
0x0
0x1
1
read-write
WPRI
SIE
Supervisor mode Interrupt Enable
Global interrupt-enable bit for Supervisor mode.
1
0x0
0x1
1
read-write
WPRI0
Reserved Writes Preserve Values, Reads Ignore Value
Reserved Writes Preserve Values, Reads Ignore Value
0
0x0
0x1
1
read-write
WPRI
M
misa
Machine ISA
The misa CSR is reporting the ISA supported by the hart.
'h301
32
read-write
MXL
Machine XLEN
The MXL field encodes the native base integer ISA width.
30
0x1
0x3
2
read-write
XLEN_32
1
XLEN_64
2
XLEN_128
3
WARL
Extensions
Extensions
The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet.
0
0x141104
0x3ffffff
26
read-write
A
Atomic extension.
1
B
*Tentatively reserved for Bit-Manipulation extension.*
2
C
Compressed extension.
4
D
Double-precision floating-point extension.
8
E
RV32E base ISA.
16
F
Single-precision floating-point extension.
32
G
*Reserved.*
64
H
Hypervisor extension.
128
I
RV32I/64I/128I base ISA.
256
J
*Tentatively reserved for Dynamically Translated Languages extension.*
512
K
*Reserved.*
1024
L
*Reserved.*
2048
M
Integer Multiply/Divide extension.
4096
N
*Tentatively reserved for User-Level Interrupts extension.*
8192
O
*Reserved.*
16384
P
*Tentatively reserved for Packed-SIMD extension.*
32768
Q
Quad-precision floating-point extension.
65536
R
*Reserved.*
131072
S
Supervisor mode implemented.
262144
T
*Reserved.*
524288
U
User mode implemented.
1048576
V
*Tentatively reserved for Vector extension.*
2097152
W
*Reserved.*
4194304
X
Non-standard extensions present.
8388608
Y
*Reserved.*
16777216
Z
*Reserved.*
33554432
WARL
M
medeleg
Machine Exception Delegation
Provides individual read/write bits to indicate that certain exceptions should be processed directly by a lower privilege level.
'h302
32
read-write
Synchronous_Exceptions
Synchronous Exceptions
There is a bit position allocated for every synchronous exception, with the index of the bit position equal to the value returned in the ``mcause`` register.
0
0x0
0xffffffff
32
read-write
WARL
M
mideleg
Machine Interrupt Delegation
Provides individual read/write bits to indicate that certain interrupts should be processed directly by a lower privilege level.
'h303
32
read-write
Interrupts
Interrupts
This bitfield holds trap delegation bits for individual interrupts, with the layout of bits matching those in the ``mip`` register.
0
0x0
0xffffffff
32
read-write
M
mie
Machine Interrupt Enable
This register contains machine interrupt enable bits.
'h304
32
read-write
Reserved_12
Reserved
Reserved.``Legal Values:``0.
12
0x0
0x1
4
read-write
WARL
MEIE
M-mode External Interrupt Enable
Enables machine mode external interrupts.
11
0x0
0x1
1
read-write
WARL
Reserved_10
Reserved
Reserved.``Legal Values:``0.
10
0x0
0x1
1
read-write
WARL
SEIE
S-mode External Interrupt Enable
Enables supervisor mode external interrupts.
9
0x0
0x1
1
read-write
WARL
UEIE
enables U-mode external interrupts.``Legal Values:``0.
8
0x0
0x1
1
read-write
WARL
MTIE
M-mode Timer Interrupt Enable
Enables machine mode timer interrupts.
7
0x0
0x1
1
read-write
WARL
Reserved_6
Reserved
Reserved.``Legal Values:``0.
6
0x0
0x1
1
read-write
WARL
STIE
S-mode Timer Interrupt Enable
Enables supervisor mode timer interrupts.
5
0x0
0x1
1
read-write
WARL
UTIE
timer interrupt-enable bit for U-mode.``Legal Values:``0.
4
0x0
0x1
1
read-write
WARL
MSIE
M-mode Software Interrupt Enable
Enables machine mode software interrupts.
3
0x0
0x1
1
read-write
Reserved_2
Reserved
Reserved.``Legal Values:``0.
2
0x0
0x1
1
read-write
WARL
SSIE
S-mode Software Interrupt Enable
Enables supervisor mode software interrupts.
1
0x0
0x1
1
read-write
WARL
USIE
enable U-mode software interrrupts.``Legal Values:``0.
0
0x0
0x1
1
read-write
WARL
M
mtvec
Machine Trap Vector
This register holds trap vector configuration, consisting of a vector base address and a vector mode.
'h305
32
read-write
BASE
The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.
2
0x0
0x3fffffff
30
read-write
WARL
MODE
Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0,1.
0
0x0
0x3
2
read-write
Direct
All exceptions set ``pc`` to BASE.
0
Vectored
Asynchronous interrupts set ``pc`` to BASE+4×cause.
1
Reserved_2
*Reserved.*
2
Reserved_3
*Reserved.*
3
WARL
M
mcountern
Machine Counter Enable
This register controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode.
'h306
32
read-write
HPMn
Hpmcountern
When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
3
0x0
0x1fffffff
29
read-write
WARL
IR
Instret
When IR is clear, attempts to read the ``instret`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
2
0x0
0x1
1
read-write
TM
Time
When TM is clear, attempts to read the ``time`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
1
0x0
0x1
1
read-write
CY
Cycle
When CY is clear, attempts to read the ``cycle`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
0
0x0
0x1
1
read-write
M
hpmevent
Hardware Performance-Monitoring Event Selector
This register controls which event causes the corresponding counter to increment.
6
'h323
32
read-write
mhpmevent
event selector CSRs
0
0x0
0x1f
5
read-write
WARL
M
mscratch
Machine Scratch
This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception.
'h340
32
read-write
mscratch
Machine Scratch
Holds a value dedicated to Machine mode.
0
0x0
0xffffffff
32
read-write
M
mepc
Machine Exception Program Counter
This register must be able to hold all valid virtual addresses.
'h341
32
read-write
mepc
Machine Exception Program Counter
When a trap is taken into M-mode, ``mepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception.
0
0x0
0xffffffff
32
read-write
WARL
M
mcause
Machine Cause
When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap.

Machine cause register (``mcause``) values after trap are shown in the following table. ========= ============== ============================== Interrupt Exception Code Description ========= ============== ============================== 1 0 *Reserved* 1 1 Supervisor software interrupt 1 2-4 *Reserved* 1 5 Supervisor timer interrupt 1 6-8 *Reserved* 1 9 Supervisor external interrupt 1 10-15 *Reserved* 1 ≥16 *Designated for platform use* 0 0 Instruction address misaligned 0 1 Instruction access fault 0 2 Illegal instruction 0 3 Breakpoint 0 4 Load address misaligned 0 5 Load access fault 0 6 Store/AMO address misaligned 0 7 Store/AMO access fault 0 8 Environment call from U-mode 0 9 Environment call from S-mode 0 10-11 *Reserved* 0 12 Instruction page fault 0 13 Load page fault 0 14 *Reserved* 0 15 Store/AMO page fault 0 16-23 *Reserved* 0 24-31 *Designated for custom use* 0 32-47 *Reserved* 0 48-63 *Designated for custom use* 0 ≥64 *Reserved* ========= ============== ==============================
'h342
32
read-write
Interrupt
Interrupt
This bit is set if the trap was caused by an interrupt.
31
0x0
0x1
1
read-write
exception_code
Exception Code
This field contains a code identifying the last exception or interrupt.
0
0x0
0x7fffffff
31
read-write
WLRL
M
mtval
Machine Trap Value
When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap.
'h343
32
read-write
mtval
Machine Trap Value
If ``mtval`` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address.

If ``mtval`` is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then ``mtval`` will contain the virtual address of the portion of the access that caused the fault.

If ``mtval`` is written with a nonzero value when an instruction access-fault or page-fault exception occurs on a system with variable-length instructions, then ``mtval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``mepc`` will point to the beginning of the instruction.
0
0x0
0xffffffff
32
read-write
WARL
M
mip
Machine Interrupt Pending
This register contains machine interrupt pending bits.
'h344
32
true
read-write
Reserved_12
Reserved
Reserved.``Legal Values:``0.
12
0x0
0x1
4
read-write
WARL
MEIP
M-mode External Interrupt Pending
The interrupt-pending bit for machine-level external interrupts.
11
0x0
0x1
1
true
read-only
Reserved_10
Reserved
Reserved.``Legal Values:``0.
10
0x0
0x1
1
read-write
WARL
SEIP
S-mode External Interrupt Pending
The interrupt-pending bit for supervisor-level external interrupts.
9
0x0
0x1
1
read-write
UEIP
enables external interrupts.``Legal Values:``0.
8
0x0
0x1
1
read-write
MTIP
M-mode Timer Interrupt Pending
The interrupt-pending bit for machine-level timer interrupts.
7
0x0
0x1
1
true
read-only
Reserved_6
Reserved
Reserved.``Legal Values:``0.
6
0x0
0x1
1
read-write
WARL
STIP
S-mode Timer Interrupt Pending
The interrupt-pending bit for supervisor-level timer interrupts.
5
0x0
0x1
1
read-write
UTIP
Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0.
4
0x0
0x1
1
read-write
MSIP
M-mode Software Interrupt Pending
The interrupt-pending bit for machine-level software interrupts.
3
0x0
0x1
1
true
read-only
Reserved_2
Reserved
Reserved.``Legal Values:``0.
2
0x0
0x1
1
read-write
WARL
SSIP
S-mode Software Interrupt Pending
The interrupt-pending bit for supervisor-level software interrupts.
1
0x0
0x1
1
read-write
USIP
A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0.
0
0x0
0x1
1
read-write
M
pmpcfg0
Physical Memory Protection Config 0
Holds configuration 0-3.
'h3A0
32
read-write
pmp3cfg
Physical Memory Protection 3 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp2cfg
Physical Memory Protection 2 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp1cfg
Physical Memory Protection 1 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp0cfg
Physical Memory Protection 0 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpcfg1
Physical Memory Protection Config 1
Holds configuration 4-7.
'h3A1
32
read-write
pmp7cfg
Physical Memory Protection 7 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp6cfg
Physical Memory Protection 6 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp5cfg
Physical Memory Protection 5 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp4cfg
Physical Memory Protection 4 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpcfg2
Physical Memory Protection Config 2
Holds configuration 8-11.
'h3A2
32
read-write
pmp11cfg
Physical Memory Protection 11 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp10cfg
Physical Memory Protection 10 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp9cfg
Physical Memory Protection 9 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp8cfg
Physical Memory Protection 8 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpcfg3
Physical Memory Protection Config 3
Holds configuration 12-15.
'h3A3
32
read-write
pmp15cfg
Physical Memory Protection 15 Config
Holds the configuration.
24
0x0
0xff
8
read-write
pmp14cfg
Physical Memory Protection 14 Config
Holds the configuration.
16
0x0
0xff
8
read-write
pmp13cfg
Physical Memory Protection 13 Config
Holds the configuration.
8
0x0
0xff
8
read-write
pmp12cfg
Physical Memory Protection 12 Config
Holds the configuration.
0
0x0
0xff
8
read-write
M
pmpaddr
Physical Memory Protection Address
Address register for Physical Memory Protection.
16
'h3B0
32
read-write
address
Address
Encodes bits 33-2 of a 34-bit physical address.
0
0x0
0xffffffff
32
read-write
WARL
M
icache
Instuction Cache
Custom Register to enable/disable for Icache [bit 0]
'h7C0
32
read-write
icache
Instruction Cache
Custom Register
0
0x1
0x1
1
read-write
M
dcache
Data Cache
Custom Register to enable/disable for Dcache [bit 0]
'h7C1
32
read-write
dcache
Data Cache
Custom Register
0
0x1
0x1
1
read-write
M
tselect
Trigger Select
This register determines which trigger is accessible through the other trigger registers.
'h7A0
32
read-write
index
Index
The set of accessible triggers must start at 0, and be contiguous.

Writes of values greater than or equal to the number of supported triggers may result in a different value in this register than what was written. To verify that what they wrote is a valid index, debuggers can read back the value and check that ``tselect`` holds what they wrote.

Since triggers can be used both by Debug Mode and M-mode, the debugger must restore this register if it modifies it.
0
0x0
0xffffffff
32
read-write
D
tdata1
Trigger Data 1
Trigger-specific data.
'h7A1
32
read-write
type
Type
Type of trigger.
28
0x0
0xf
4
read-write
no_trigger
There is no trigger at this ``tselect``.
0
legacy_address_match_trigger
The trigger is a legacy SiFive address match trigger. These should not be implemented and aren’t further documented here.
1
address_data_match_trigger
The trigger is an address/data match trigger. The remaining bits in this register act as described in ``mcontrol``.
2
instruction_count_trigger
The trigger is an instruction count trigger. The remaining bits in this register act as described in ``icount``.
3
interrupt_trigger
The trigger is an interrupt trigger. The remaining bits in this register act as described in ``itrigger``.
4
exception_trigger
The trigger is an exception trigger. The remaining bits in this register act as described in ``etrigger``.
5
Reserved_6
*Reserved.*
6
Reserved_7
*Reserved.*
7
Reserved_8
*Reserved.*
8
Reserved_9
*Reserved.*
9
Reserved_10
*Reserved.*
10
Reserved_11
*Reserved.*
11
Reserved_12
*Reserved.*
12
Reserved_13
*Reserved.*
13
Reserved_14
*Reserved.*
14
trigger_exists
This trigger exists (so enumeration shouldn’t terminate), but is not currently available.
15
dmode
Debug Mode
This bit is only writable from Debug Mode.
27
0x0
0x1
1
read-write
D_and_M_mode
Both Debug and M-mode can write the ``tdata`` registers at the selected ``tselect``.
0
M_mode_only
Only Debug Mode can write the ``tdata`` registers at the selected ``tselect``. Writes from other modes are ignored.
1
data
Data
Trigger-specific data.
0
0x0
0x7ffffff
27
read-write
D
tdata2
Trigger Data 2
Trigger-specific data.
'h7A2
32
read-write
data
Data
Trigger-specific data.
0
0x0
0xffffffff
32
read-write
D
tdata3
Trigger Data 3
Trigger-specific data.
'h7A3
32
read-write
data
Data
Trigger-specific data.
0
0x0
0xffffffff
32
read-write
D
tinfo
Trigger Info
Shows trigger information.
'h7A4
32
true
read-only
info
Info
One bit for each possible ``type`` enumerated in ``tdata1``. Bit N corresponds to type N. If the bit is set, then that type is supported by the currently selected trigger.

If the currently selected trigger doesn’t exist, this field contains 1.

If ``type`` is not writable, this register may be unimplemented, in which case reading it causes an illegal instruction exception. In this case the debugger can read the only supported type from ``tdata1``.
0
0x0
0xffff
16
true
read-only
D
dcsr
Debug Control and Status
Debug ontrol and status register.
'h7B0
32
true
read-write
xdebugver
Debug Version
Shows the version of the debug support.
28
0x0
0xf
4
true
read-only
no_ext_debug
There is no external debug support.
0
ext_debug_spec
External debug support exists as it is described in the riscv-debug-release document.
4
ext_debug_no_spec
There is external debug support, but it does not conform to any available version of the riscv-debug-release spec.
15
ebreakm
Environment Breakpoint M-mode
Shows the behvior of the ``ebreak`` instruction in machine mode.
15
0x0
0x1
1
read-write
break_as_spec
``ebreak`` instructions in M-mode behave as described in the Privileged Spec.
0
break_to_debug
``ebreak`` instructions in M-mode enter Debug Mode.
1
ebreaks
Environment Breakpoint S-mode
Shows the behvior of the ``ebreak`` instruction in supervisor mode.
13
0x0
0x1
1
read-write
break_as_spec
``ebreak`` instructions in S-mode behave as described in the Privileged Spec.
0
break_to_debug
``ebreak`` instructions in S-mode enter Debug Mode.
1
ebreaku
Environment Breakpoint U-mode
Shows the behvior of the ``ebreak`` instruction in user mode.
12
0x0
0x1
1
read-write
break_as_spec
``ebreak`` instructions in U-mode behave as described in the Privileged Spec.
0
break_to_debug
``ebreak`` instructions in U-mode enter Debug Mode.
1
stepie
Stepping Interrupt Enable
Enables/disables interrupts for single stepping.

The debugger must not change the value of this bit while the hart is running.
11
0x0
0x1
1
read-write
disabled
Interrupts are disabled during single stepping.
0
enabled
Interrupts are enabled during single stepping.
1
WARL
stopcount
Stop Counters
Starts/stops incrementing counters in debug mode.
10
0x0
0x1
1
read-write
increment_counters
Increment counters as usual.
0
dont_increment_counters
Don’t increment any counters while in Debug Mode or on ``ebreak`` instructions that cause entry into Debug Mode.
1
WARL
stoptime
Stop Timers
Starts/stops incrementing timers in debug mode.
9
0x0
0x1
1
read-write
increment_timers
Increment timers as usual.
0
dont_increment_timers
Don’t increment any hart-local timers while in Debug Mode.
1
WARL
cause
Cause
Explains why Debug Mode was entered.

When there are multiple reasons to enter Debug Mode in a single cycle, hardware sets ``cause`` to the cause with the highest priority.
6
0x0
0x7
3
read-write
ebreak_instruction
An ``ebreak`` instruction was executed. (priority 3)
1
trigger_module
The Trigger Module caused a breakpoint exception. (priority 4, highest)
2
debugger_request
The debugger requested entry to Debug Mode using ``haltreq``. (priority 1)
3
single_step
The hart single stepped because ``step`` was set. (priority 0, lowest)
4
reset_halt
The hart halted directly out of reset due to ``resethaltreq``. It is also acceptable to report 3 when this happens. (priority 2)
5
mprven
Modify Privilege Enable
Enables/disables the modify privilege setting in debug mode.
4
0x0
0x1
1
read-write
disable_mprv
MPRV in ``mstatus`` is ignored in Debug Mode.
0
enable_mprv
MPRV in ``mstatus`` takes effect in Debug Mode.
1
WARL
nmip
Non-Maskable Interrupt Pending
When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
3
0x0
0x1
1
true
read-only
step
Step
When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. The debugger must not change the value of this bit while the hart is running.
2
0x0
0x1
1
read-write
prv
Privilege level
Contains the privilege level the hart was operating in when Debug Mode was entered. A debugger can change this value to change the hart’s privilege level when exiting Debug Mode.
0
0x0
0x3
2
read-write
User
0
Supervisor
1
Machine
3
D
dpc
Debug PC
Upon entry to debug mode, ``dpc`` is updated with the virtual address of the next instruction to be executed.

When resuming, the hart’s PC is updated to the virtual address stored in ``dpc``. A debugger may write ``dpc`` to change where the hart resumes.
'h7B1
32
read-write
dpc
The ``dpc`` behavior is described in more detail in the table below.

.. csv-table:: :header: "Cause", "Virtual Address in DPC"

"``ebreak``", "Address of the ``ebreak`` instruction." "single step", "Address of the instruction that would be executed next if no debugging was going on. Ie. pc + 4 for 32-bit instructions that don’t change program flow, the destination PC on taken jumps/branches, etc." "trigger module", "If ``timing`` is 0, the address of the instruction which caused the trigger to fire. If ``timing`` is 1, the address of the next instruction to be executed at the time that debug mode was entered." "halt request", "Address of the next instruction to be executed at the time that debug mode was entered."
0
0x0
0xffffffff
32
read-write
D
dscratch
Debug Scratch Register
Optional scratch register. A debugger must not write to this register unless ``hartinfo`` explicitly mentions it.
2
'h7B2
32
read-write
dscratch
0
0x0
0xffffffff
32
read-write
D
ftran
Floating Point Custom CSR
'h800
32
read-write
ftran
Floating Point Custom CSR
0
0x0
0x7f
7
read-write
U
mcycle
M-mode Cycle counter
Counts the number of clock cycles executed by the processor core on which the hart is running.
'hB00
32
read-write
count
Count
Counts the number of clock cycles executed by the processor core.
0
0x0
0xffffffff
32
read-write
M
minstret
Machine Instruction Retired counter
Counts the number of instructions the hart has retired.
'hB02
32
read-write
count
Count
Counts the number of instructions the hart has retired.
0
0x0
0xffffffff
32
read-write
M
ml1_icache_miss
L1 Inst Cache Miss
Hardware performance event counter.
'hB03
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
ml1_dcache_miss
L1 Data Cache Miss
Hardware performance event counter.
'hB04
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mitlb_miss
ITLB Miss
Hardware performance event counter.
'hB05
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mdtlb_miss
DTLB Miss
Hardware performance event counter.
'hB06
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mload
Loads
Hardware performance event counter.
'hB07
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mstore
Stores
Hardware performance event counter.
'hB08
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mexception
Taken Exceptions
Hardware performance event counter.
'hB09
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mexception_ret
Exception Return
Hardware performance event counter.
'hB0A
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mbranch_jump
Software Change of PC
Hardware performance event counter.
'hB0B
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mcall
Procedure Call
Hardware performance event counter.
'hB0C
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mret
Procedure Return
Hardware performance event counter.
'hB0D
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mmis_predict
Branch mis-predicted
Hardware performance event counter.
'hB0E
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
msb_full
Scoreboard Full
Hardware performance event counter.
'hB0F
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mif_empty
Instruction Fetch Queue Empty
Hardware performance event counter.
'hB10
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
mcycleh
Upper 32-bits of M-mode Cycle counter
Counts the number of clock cycles executed by the processor core on which the hart is running.
'hB80
32
read-write
count
Count
Counts the number of clock cycles executed by the processor core.
0
0x0
0xffffffff
32
read-write
M
minstreth
Upper 32-bits of Machine Instruction Retired counter
Counts the number of instructions the hart has retired.
'hB82
32
read-write
count
Count
Counts the number of instructions the hart has retired.
0
0x0
0xffffffff
32
read-write
M
mhpmcounterh
Upper 32-bits of Machine Hardware Performance Monitoring Counter
Hardware performance event counter.
6
'hB83
32
read-write
count
Count
0
0x0
0xffffffff
32
read-write
M
cycle
Cycle counter
Cycle counter for RDCYCLE instruction.
'hC00
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
U
time
Timer
Timer for RDTIME instruction.
'hC01
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
instret
Instruction Retired counter
Instructions-retired counter for RDINSTRET instruction
'hC02
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
U
l1_icache_miss
L1 Inst Cache Miss
Hardware performance event counter.
'hC03
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
l1_dcache_miss
L1 Data Cache Miss
Hardware performance event counter.
'hC04
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
itlb_miss
ITLB Miss
Hardware performance event counter.
'hC05
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
dtlb_miss
DTLB Miss
Hardware performance event counter.
'hC06
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
load
Loads
Hardware performance event counter.
'hC07
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
store
Stores
Hardware performance event counter.
'hC08
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
exception
Taken Exceptions
Hardware performance event counter.
'hC09
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
exception_ret
Exception Return
Hardware performance event counter.
'hC0A
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
branch_jump
Software Change of PC
Hardware performance event counter.
'hC0B
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
call
Procedure Call
Hardware performance event counter.
'hC0C
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
ret
Procedure Return
Hardware performance event counter.
'hC0D
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
mis_predict
Branch mis-predicted
Hardware performance event counter.
'hC0E
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
sb_full
Scoreboard Full
Hardware performance event counter.
'hC0F
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
if_empty
Instruction Fetch Queue Empty
Hardware performance event counter.
'hC10
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
M
cycleh
Upper 32-bits of Cycle counter
Cycle counter for RDCYCLE instruction.
'hC80
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
U
timeh
Upper 32-bit of Timer
Timer for RDTIME instruction.
'hC81
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
instreth
Upper 32-bits of Instruction Retired counter
Instructions-retired counter for RDINSTRET instruction
'hC82
32
true
read-only
count
Count
0
0x0
0xffffffff
32
true
read-only
U
mvendorid
Machine Vendor ID
This register provids the JEDEC manufacturer ID of the provider of the core.
'hF11
32
true
read-only
bank
Bank
Contain encoding for number of one-byte continuation codes discarding the parity bit.
7
0x0
0x1ffffff
25
true
read-only
offset
Offset
Contain encording for the final byte discarding the parity bit.
0
0x0
0x7f
7
true
read-only
M
marchid
Machine Architecture ID
This register encodes the base microarchitecture of the hart.
'hF12
32
true
read-only
architecture_id
Architecture ID
Provide Encoding the base microarchitecture of the hart.
0
0x3
0xffffffff
32
true
read-only
M
mimpid
Machine Implementation ID
Provides a unique encoding of the version of the processor implementation.
'hF13
32
true
read-only
implementation
Implementation
Provides unique encoding of the version of the processor implementation.
0
0x0
0xffffffff
32
true
read-only
M
mhartid
Machine Hardware Thread ID
This register contains the integer ID of the hardware thread running the code.
'hF14
32
true
read-only
hart_id
Hart ID
Contains the integer ID of the hardware thread running the code.
0
0x0
0xffffffff
32
true
read-only
M
32