TOP_LEVEL_ENTITY cva6_altera
ORIGINAL_QUARTUS_VERSION 24.1.0
PROJECT_CREATION_TIME_DATE "14:07:44  JUNE 03, 2024"
LAST_QUARTUS_VERSION "24.1.0 Pro Edition"
PROJECT_OUTPUT_DIRECTORY output_files
MIN_CORE_JUNCTION_TEMP 0
MAX_CORE_JUNCTION_TEMP 100
DEVICE AGFB014R24B2E2V
FAMILY "Agilex 7"
ERROR_CHECK_FREQUENCY_DIVISOR 256
EDA_SIMULATION_TOOL "QuestaSim (Verilog)"
EDA_TIME_SCALE "1 ps" -section_id eda_simulation
EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
USE_CONFIGURATION_DEVICE ON
GENERATE_PR_RBF_FILE ON
ENABLE_ED_CRC_CHECK ON
MINIMUM_SEU_INTERVAL 0
PWRMGT_SLAVE_DEVICE_TYPE ED8401
PWRMGT_SLAVE_DEVICE0_ADDRESS 47
PWRMGT_SLAVE_DEVICE1_ADDRESS 00
PWRMGT_SLAVE_DEVICE2_ADDRESS 00
ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
USE_PWRMGT_SCL SDM_IO14
USE_PWRMGT_SDA SDM_IO11
USE_CONF_DONE SDM_IO16
AUTO_RESTART_CONFIGURATION OFF
USE_CVP_CONFDONE SDM_IO10
DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
PWRMGT_PAGE_COMMAND_ENABLE OFF
PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
PWRMGT_LINEAR_FORMAT_N "-13"
POWER_APPLY_THERMAL_MARGIN ADDITIONAL
USE_INIT_DONE SDM_IO0
BOARD default
OPTIMIZATION_MODE "OPTIMIZE NETLIST FOR ROUTABILITY"
ALM_REGISTER_PACKING_EFFORT "LOW"
ADVANCED_PHYSICAL_SYNTHESIS "ON"
PLACEMENT_EFFORT_MULTIPLIER 50
ROUTER_TIMING_OPTIMIZATION_LEVEL "MAXIMUM"
FINAL_PLACEMENT_OPTIMIZATION "AUTOMATICALLY"
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
GLOBAL_PLACEMENT_EFFORT "MAXIMUM EFFORT"
QII_AUTO_PACKED_REGISTERS SPARSE
OPTIMIZATION_TECHNIQUE SPEED
