!Feature
next_elt_id: 5
name: RV32Zcb Load and Store Instructions
id: 18
display_order: 18
subfeatures: !!omap
- 000_C.LBU: !Subfeature
    name: 000_C.LBU
    tag: VP_ISA_RV32 EMBEDDED_F017_S000
    next_elt_id: 3
    display_order: 0
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32 EMBEDDED_F017_S000_I000
        description: "c.lbu rd', uimm(rs1')\nx[8 + rd'] = zext(M[x[8 + rd'] + zext(uimm[1:0])][7:0])"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rd' register are used\nAll
          possible rs1' register are used\nALl possible combinations where rd' ==
          rs1' are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32 EMBEDDED_F017_S000_I001
        description: "c.lbu rd', uimm(rs1')\nx[8 + rd'] = zext(M[x[8 + rd'] + zext(uimm[1:0])][7:0])"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits
          of uimm are toggled\nAll bits of rs1' are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32 EMBEDDED_F017_S000_I002
        description: "c.lbu rd', uimm(rs1')\nx[8 + rd'] = zext(M[x[8 + rd'] + zext(uimm[1:0])][7:0])"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd' value is non-zero and zero\nAll bits of
          rd' are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
- 001_C.SB: !Subfeature
    name: 001_C.SB
    tag: VP_ISA_RV32 EMBEDDED_F017_S001
    next_elt_id: 3
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32 EMBEDDED_F017_S001_I000
        description: "c.sb rs1', uimm(rs2')\nM[x[8 + rs1'] + zext(uimm[1:0])][7:0]
          = x[8 + rs2']"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1' register are used\n
          All possible rs2' register are used\nAll possible combinations where rs1'
          = rs2' register are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32 EMBEDDED_F017_S001_I001
        description: "c.sb rs1', uimm(rs2')\nM[x[8 + rs1'] + zext(uimm[1:0])][7:0]
          = x[8 + rs2']"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits
          of uimm are toggled\nAll bits of rs1' are toggled\nAll bits of rs2' are
          toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
- 002_C.LHU: !Subfeature
    name: 002_C.LHU
    tag: VP_ISA_RV32 EMBEDDED_F017_S002
    next_elt_id: 3
    display_order: 2
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32 EMBEDDED_F017_S002_I000
        description: "c.lhu rd', uimm(rs1')\nx[8 + rd'] = zext(M[x[8 + rd'] + zext(uimm[1])][15:0])"
        reqt_doc: ./RISCV_Instructions
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rd' register are used\nAll
          possible rs1' register are used\nALl possible combinations where rd' ==
          rs1' are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32 EMBEDDED_F017_S002_I001
        description: "c.lhu rd', uimm(rs1')\nx[8 + rd'] = zext(M[x[8 + rd'] + zext(uimm[1])][15:0])"
        reqt_doc: ./RISCV_Instructions
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits
          of uimm are toggled\nAll bits of rs1' are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32 EMBEDDED_F017_S002_I002
        description: "c.lhu rd', uimm(rs1')\nx[8 + rd'] = zext(M[x[8 + rd'] + zext(uimm[1])][15:0])"
        reqt_doc: ./RISCV_Instructions
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd' value is non-zero and zero\nAll bits of
          rd' are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
- 003_C.LH: !Subfeature
    name: 003_C.LH
    tag: VP_ISA_RV32 EMBEDDED_F017_S003
    next_elt_id: 3
    display_order: 3
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32 EMBEDDED_F017_S003_I000
        description: "c.lh rd', uimm(rs1')\nx[8 + rd'] = sext(M[x[8 + rd'] + zext(uimm[1])][15:0])"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rd' register are used\nAll
          possible rs1' register are used\nALl possible combinations where rd' ==
          rs1' are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32 EMBEDDED_F017_S003_I001
        description: "c.lh rd', uimm(rs1')\nx[8 + rd'] = sext(M[x[8 + rd'] + zext(uimm[1])][15:0])"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits
          of uimm are toggled\nAll bits of rs1' are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '002': !VerifItem
        name: '002'
        tag: VP_ISA_RV32 EMBEDDED_F017_S003_I002
        description: "c.lh rd', uimm(rs1')\nx[8 + rd'] = sext(M[x[8 + rd'] + zext(uimm[1])][15:0])"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Output result:\n\nrd' value is non-zero and zero\nAll bits of
          rd' are toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
- 004_C.SH: !Subfeature
    name: 004_C.SH
    tag: VP_ISA_RV32 EMBEDDED_F017_S004
    next_elt_id: 2
    display_order: 4
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_ISA_RV32 EMBEDDED_F017_S004_I000
        description: "c.sh rs1', uimm(rs2')\nM[x[8 + rs1'] + zext(uimm[1])][15:0]
          = x[8 + rs2']"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Register operands:\n\nAll possible rs1' register are used\n
          All possible rs2' register are used\nAll possible combinations where rs1'
          = rs2' are used"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: 56
        coverage_loc: ''
        comments: ''
    - '001': !VerifItem
        name: '001'
        tag: VP_ISA_RV32 EMBEDDED_F017_S004_I001
        description: "c.sh rs1', uimm(rs2')\nM[x[8 + rs1'] + zext(uimm[1])][15:0]
          = x[8 + rs2']"
        reqt_doc: ./RISCV_Instructions.rst
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits
          of uimm are toggled\nAll bits of rs1' are toggled\nAll bits of rs2' are
          toggled"
        pfc: -1
        test_type: -1
        cov_method: -1
        cores: 56
        coverage_loc: ''
        comments: ''
vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $'
io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $'
config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $'
ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $'
