// Copyright 2023 Thales 
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

- csr: CSR_MSTATUS
  description: >
    Machine Status Register
  address: 0x300
  privilege_mode: M
  rv32:
    - field_name: SD
      description: >
       SD 
      type: R
      reset_val: 0
      msb: 31
      lsb: 31
    - field_name: WPRI
      description: >
       reserved for future use 
      type: R
      reset_val: 0
      msb: 30
      lsb: 23
    - field_name: TSR
      description: >
       Trap SRET: supports intercepting the supervisor exception return instruction
      type: RW
      reset_val: 0
      msb: 22
      lsb: 22
    - field_name: TW
      description: >
       Timeout Wait: supports intercepting the WFI instruction 
      type: RW
      reset_val: 0
      msb: 21
      lsb: 21
    - field_name: TVM
      description: >
        Trap Virtual Memory,supports intercepting supervisor virtual-memory management operations.
      type: RW
      reset_val: 0
      msb: 20
      lsb: 20
    - field_name: MXR
      description: >
        Make eXecutable Readable: modifies the privilege with which loads access virtual memory.        
      type: RW
      reset_val: 0
      msb: 19
      lsb: 19
    - field_name: SUM
      description: >
        permit Supervisor User Memory access
      type: RW
      reset_val: 0
      msb: 18
      lsb: 18
    - field_name: MPRV
      description: >
       Modify PRiVilege 
      type: RW
      reset_val: 0
      msb: 17
      lsb: 17
    - field_name: XS
      description: >
        use to reduce the cost of context save and restore by setting and tracking the current state
      type: R
      reset_val: 0
      msb: 16
      lsb: 15
    - field_name: FS
      description: >
       use to reduce the cost of context save and restore by setting and tracking the current state 
      type: RW
      reset_val: 0
      msb: 14
      lsb: 13
    - field_name: MPP
      description: >
        xPP fields can only hold privilege modes up to x, so MPP is two bits wide, SPP is one bit wide, and UPP is implicitly zero 
      type: RW
      reset_val: 0
      msb: 12
      lsb: 11
    - field_name: VS
      description: >
       Vector Extension state 
      type: RW
      reset_val: 0
      msb: 10
      lsb: 9
    - field_name: SPP
      description: >
       xPP fields can only hold privilege modes up to x, so MPP is two bits wide, SPP is one bit wide, and UPP is implicitly zero  
      type: RW
      reset_val: 0
      msb: 8
      lsb: 8
    - field_name: MPIE
      description: >
        MPIE       
      type: RW
      reset_val: 0
      msb: 7
      lsb: 7
    - field_name: UBE
      description: >
       User break point Enable
      type: R
      reset_val: 0
      msb: 6
      lsb: 6
    - field_name: SPIE
      description: >
        indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode        
      type: RW
      reset_val: 0
      msb: 5
      lsb: 5
    - field_name: UPIE
      description: >
        indicates whether user-level interrupts were enabled prior to taking a user-level trap
      type: R
      reset_val: 0
      msb: 4
      lsb: 4
    - field_name: MIE
      description: >
       Global interrupt-enable bits 
      type: RW
      reset_val: 0
      msb: 3
      lsb: 3
    - field_name: WPRI
      description: >
       reserved for future use 
      type: R
      reset_val: 0
      msb: 2
      lsb: 2
    - field_name: SIE
      description: >
       Global interrupt-enable bits 
      type: RW
      reset_val: 0
      msb: 1
      lsb: 1
    - field_name: UIE
      description: >
       Global interrupt-enable bits 
      type: R
      reset_val: 0
      msb: 0
      lsb: 0
 
- csr: CSR_MISA
  description: >
    ISA and extensions
  address: 0x301
  privilege_mode: M
  rv32:
    - field_name: MXL
      description: >
        MXL
      type: R
      reset_val: 0
      msb: 31
      lsb: 31
    - field_name: MXL
      description: >
         MXL
      type: R
      reset_val: 1
      msb: 30
      lsb: 30
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 29
      lsb: 24
    - field_name: Non-standard extensions present
      description: >
       Non-standard extensions present
      type: R
      reset_val: 0
      msb: 23
      lsb: 23
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 22
      lsb: 21
    - field_name: User mode implemented
      description: >
       User mode implemented
      type: R
      reset_val: 1
      msb: 20
      lsb: 20
    - field_name:  Reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 19
      lsb: 19
    - field_name: Supervisor mode implemented
      description: >
        Supervisor mode implemented
      type: R
      reset_val: 1
      msb: 18
      lsb: 18
    - field_name: Reserved
      description: >
       Reserved for future use 
      type: R
      reset_val: 0
      msb: 17
      lsb: 13
    - field_name: Integer Multiply/Divide extension
      description: >
        Integer Multiply/Divide extension
      type: R
      reset_val: 1
      msb: 12
      lsb: 12
    - field_name: Reserved
      description: >
       reserved for future use 
      type: R
      reset_val: 0
      msb: 11
      lsb: 9
    - field_name: RV32I/64I/128I base ISA
      description: >
       RV32I/64I/128I base ISA  
      type: R
      reset_val: 1
      msb: 8
      lsb: 8
    - field_name: Hypervisoe Extension
      description: >
        Hypervisor Extension      
      type: R
      reset_val: 0
      msb: 7
      lsb: 7
    - field_name: Reserved
      description: >
       reserved for future use 
      type: R
      reset_val: 0
      msb: 6
      lsb: 6
    - field_name: Single precision FP Extension
      description: >
        Single precision FP extension       
      type: R
      reset_val: 0
      msb: 5
      lsb: 5
    - field_name: RV32E base ISA
      description: >
        RV32E base ISA
      type: R
      reset_val: 0
      msb: 4
      lsb: 4
    - field_name: Double precision FP Extension
      description: >
       Double precision FP Extension
      type: R
      reset_val: 0
      msb: 3
      lsb: 3
    - field_name: Compressed Extension
      description: >
       Compressed Extension 
      type: R
      reset_val: 1
      msb: 2
      lsb: 2
    - field_name: Reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 1
      lsb: 1
    - field_name: Atomic Extension
      description: >
       Atomic Extension 
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_MIDELEG
  description: >
    Machine interrupt delegation register
  address: 0x303
  privilege_mode: M
  rv32:
    - field_name: reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 31
      lsb: 12      
    - field_name: Reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 11
      lsb: 11
    - field_name: Reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 10
      lsb: 10      
    - field_name: STI 
      description: >
       Supervisor timer interrupt 
      type: RW
      reset_val: 0
      msb: 9
      lsb: 9
    - field_name: reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 8
      lsb: 8      
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 7
      lsb: 7
    - field_name: reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 6
      lsb: 6 
    - field_name: STI
      description: >
        Supervisor timer interrupt
      type: RW
      reset_val: 0
      msb: 5
      lsb: 5
    - field_name: reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 4
      lsb: 4
    - field_name: Reserved
      description: >
        reserved for future use
      type: R
      reset_val: 0
      msb: 3
      lsb: 3
    - field_name: reserved
      description: >
       Reserved for future use
      type: R
      reset_val: 0
      msb: 2
      lsb: 2
    - field_name: Supervisor sw interrupts
      description: >
         S-mode software interrupts
      type: RW
      reset_val: 0
      msb: 1
      lsb: 1
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_MIE
  description: >
    Machine Interrupt enable register
  address: 0x304
  privilege_mode: M
  rv32:
    - field_name: Reserved
      description: >
        reserved for future use
      type: R
      reset_val: 0
      msb: 31
      lsb: 12
    - field_name: MEIE 
      description: >
       enables machine external interrupts when set 
      type: RW
      reset_val: 0
      msb: 11
      lsb: 11
    - field_name: Reserved
      description: >
        reserved for future use
      type: R
      reset_val: 0
      msb: 10
      lsb: 10
    - field_name: SEIE  
      description: >
       enable S-mode external interrupts,        
      type: RW
      reset_val: 0
      msb: 9
      lsb: 9
    - field_name: UEIE 
      description: >
       enables U-mode external interrupts
      type: R
      reset_val: 0
      msb: 8
      lsb: 8
    - field_name: MTIE 
      description: >
       timer interrupt-enable bit for M-mode 
      type: RW
      reset_val: 0
      msb: 7
      lsb: 7
   - field_name: Reserved
      description: >
        reserved for future use
      type: R
      reset_val: 0
      msb: 6
      lsb: 6    
    - field_name: STIE 
      description: >
        timer interrupt-enable bit for S-mode
      type: RW
      reset_val: 0
      msb: 5
      lsb: 5 
    - field_name: UTIE 
      description: >
        timer interrupt-enable bit for U-mode
      type: R
      reset_val: 0
      msb: 4
      lsb: 4
    - field_name: MSIE 
      description: >
       enable M-mode Software interrupts 
      type: RW
      reset_val: 0
      msb: 3
      lsb: 3
    - field_name: Reserved
      description: >
        reserved for future use
      type: R
      reset_val: 0
      msb: 2
      lsb: 2
    - field_name: SSIE 
      description: >
        enable S-mode software interrupts
      type: RW
      reset_val: 0
      msb: 1
      lsb: 1
    - field_name: USIE 
      description: >
        enable U-mode software interrrupts 
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_MTVEC
  description: >
    Machine trap-handler base address
  address: 0x305
  privilege_mode: M
  rv32:
    - field_name: BASE
      description: >
       holds trap vector configuration, 
      type: RW
      reset_val: 0
      msb: 31
      lsb: 2
    - field_name: Reserved
      description: >
        Reserved for future use    
      type: R
      reset_val: 0
      msb: 1
      lsb: 1      
    - field_name: MODE
      description: >
        impose additional alignment constraints on the value in the BASE field        
      type: RW
      reset_val: 0
      msb: 0
      lsb: 0    

- csr: CSR_MCOUNTEREN
  description: >
    Machine counter enable
  address: 0x306
  privilege_mode: M
  rv32:
    - field_name: HPMn
      description: >
        When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted.
      type: RW
      reset_val: 0
      msb: 31
      lsb: 3
    - field_name: IR
      description: >
         When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
      type: RW
      reset_val: 0
      msb: 2
      lsb: 2
    - field_name: TM
      description: >
         When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted        
      type: RW
      reset_val: 0
      msb: 1
      lsb: 1
    - field_name: CY
      description: >
         When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
      type: RW
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_MSCRATCH
  description: >
    Scratch register for machine trap handlers
  address: 0x340
  privilege_mode: M
  rv32:
    - field_name: mscratch
      description: >
        hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler
      type: RW
      reset_val: 0
      msb: 31
      lsb: 0

- csr: CSR_MEPC
  description: >
    Machine exception program counter
  address: 0x341
  privilege_mode: M
  rv32:
    - field_name: mepc
      description: >
       holds all valid physical and virtual addresses 
      type: RW
      reset_val: 0
      msb: 31
      lsb: 0

- csr: CSR_MCAUSE
  description: >
    Machine Trap cause
  address: 0x342
  privilege_mode: M
  rv32:
    - field_name: Interrupt
      description: >
       its set if the trap was caused by an interrupt 
      type: RW
      reset_val: 0
      msb: 31
      lsb: 31
    - field_name: exception code
      description: >
        hold supported exception codes        
      type: RW
      reset_val: 0
      msb: 30
      lsb: 0

- csr: CSR_MTVAL
  description: >
    Machine bad address or Instruction
  address: 0x343
  privilege_mode: M
  rv32:
    - field_name: mtval
      description: >
        When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap.        
      type: RW
      reset_val: 0
      msb: 31
      lsb: 0

- csr: CSR_MIP
  description: >
    Machine Interrupt enable register
  address: 0x344
  privilege_mode: M
  rv32:
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 31
      lsb: 12
    - field_name: MEIP
      description: >
        machine external interrupt pending
      type: R
      reset_val: 0
      msb: 11
      lsb: 11
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 10
      lsb: 10
    - field_name: SEIP  
      description: >
       enable S-mode external interrupts pending        
      type: RW
      reset_val: 0
      msb: 9
      lsb: 9
    - field_name: UEIE 
      description: >
       enables U-mode external interrupts
      type: R
      reset_val: 0
      msb: 8
      lsb: 8
    - field_name: MTIP 
      description: >
       timer interrupt-pending bit for M-mode 
      type: R
      reset_val: 0
      msb: 7
      lsb: 7
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 6
      lsb: 6
    - field_name: STIP
      description: >
        timer interrupt-pending bit for S-mode
      type: RW
      reset_val: 0
      msb: 5
      lsb: 5 
    - field_name: UTIE 
      description: >
        timer interrupt-enable bit for U-mode
      type: R
      reset_val: 0
      msb: 4
      lsb: 4
    - field_name: MSIP
      description: >
       enable M-mode Software pending 
      type: R
      reset_val: 0
      msb: 3
      lsb: 3
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 2
      lsb: 2
    - field_name: SSIP 
      description: >
        enable S-mode software pending
      type: RW
      reset_val: 0
      msb: 1
      lsb: 1
    - field_name: USIE 
      description: >
        enable U-mode software interrrupts 
      type: R
      reset_val: 0
      msb: 0
      lsb: 0   


- csr: CSR_PMPADDR0
  description: >
   PMP address registers
  address: 0x3B0
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_PMPADDR1
  description: >
   PMP address registers
  address: 0x3B1
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_PMPADDR2
  description: >
   PMP address registers
  address: 0x3B2
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_PMPADDR3
  description: >
   PMP address registers
  address: 0x3B3
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_PMPADDR4
  description: >
   PMP address registers
  address: 0x3B4
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_PMPADDR5
  description: >
   PMP address registers
  address: 0x3B5
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_PMPADDR6
  description: >
   PMP address registers
  address: 0x3B6
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_PMPADDR7
  description: >
   PMP address registers
  address: 0x3B7
  privilege_mode: M
  rv32:
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: RW
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: address
      description: >
        encodes bits 33-2 of a 34-bit physical address
      type: R
      reset_val: 0
      msb: 0
      lsb: 0

- csr: CSR_ICACHE
  description: >
   Custom Register to enable/disable for Icache [bit 0]  
  address: 0x7C0
  privilege_mode: M
  rv32:
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: ICACHE
      description: >
       Custom Register 
      type: RW
      reset_val: 1
      msb: 0
      lsb: 0

- csr: CSR_DCACHE
  description: >
   Custom Register to enable/disable for Dcache [bit 0]
  address: 0x7c1
  privilege_mode: M
  rv32:
    - field_name: Reserved
      description: >
        Reserved for future use
      type: R
      reset_val: 0
      msb: 31
      lsb: 1
    - field_name: DCACHE
      description: >
        Custom Register
      type: RW
      reset_val: 1
      msb: 0
      lsb: 0
