name: cv32e40s_corev_pma
description: CORE-V turnon regression across multiple PMA configurations

builds:
  corev-dv:
    cmd: make comp_corev-dv
    dir: cv32e40s/sim/uvmt

  corev-dv_pma_1:
    cmd: make comp_corev-dv
    cfg: pma_test_cfg_1
    dir: cv32e40s/sim/uvmt

  corev-dv_pma_2:
    cmd: make comp_corev-dv
    cfg: pma_test_cfg_2
    dir: cv32e40s/sim/uvmt

  corev-dv_pma_3:
    cmd: make comp_corev-dv
    cfg: pma_test_cfg_3
    dir: cv32e40s/sim/uvmt

  corev-dv_pma_4:
    cmd: make comp_corev-dv
    cfg: pma_test_cfg_4
    dir: cv32e40s/sim/uvmt

  corev-dv_pma_5:
    cmd: make comp_corev-dv
    cfg: pma_test_cfg_5
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s:
    cmd: make comp
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s_pma_1:
    cmd: make comp
    cfg: pma_test_cfg_1
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s_pma_2:
    cmd: make comp
    cfg: pma_test_cfg_2
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s_pma_3:
    cmd: make comp
    cfg: pma_test_cfg_3
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s_pma_4:
    cmd: make comp
    cfg: pma_test_cfg_4
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s_pma_5:
    cmd: make comp
    cfg: pma_test_cfg_5
    dir: cv32e40s/sim/uvmt

tests:
  hello-world:
    description: UVM Hello World Test
    dir: cv32e40s/sim/uvmt
    cmd: make test TEST=hello-world
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
    num: 5

  corev_rand_jump_stress_test:
    description: Generated corev-dv jump stress test
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test
    num: 5

  corev_rand_arithmetic_base_test:
    description: Generated corev-dv arithmetic test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_instr_test:
    description: Generated corev-dv random instruction test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_instr_test
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_instr_long_stall:
    description: Generated corev-dv random instruction test with long stalls
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_instr_long_stall
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_illegal_instr_test:
    description: Generated corev-dv random instruction test with illegal instructions
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_illegal_instr_test
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_jump_stress_test:
    description: Generated corev-dv jump stress test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_interrupt:
    description: Generated corev-dv random interrupt test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_interrupt
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_debug:
    description: Generated corev-dv random debug test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_debug
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_debug_single_step:
    description: debug random test with single-stepping
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_debug_single_step
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_debug_ebreak:
    description: debug random test with ebreaks from ROM
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_debug_ebreak
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_interrupt_wfi:
    description: Generated corev-dv random interrupt WFI test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_interrupt_wfi_mem_stress:
    description: Generated corev-dv random interrupt WFI test with memory stress
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi_mem_stress
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_interrupt_debug:
    description: Generated corev-dv random interrupt WFI test with debug
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_interrupt_debug
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_interrupt_exception:
    description: Generated corev-dv random interrupt WFI test with exceptions
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_interrupt_exception
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5

  corev_rand_interrupt_nested:
    description: Generated corev-dv random interrupt WFI test with random nested interrupts
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_interrupt_nested
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
      - uvmt_cv32e40s_pma_3
      - uvmt_cv32e40s_pma_4
      - uvmt_cv32e40s_pma_5
    num: 5
