name: corev_rand_interrupt
uvm_test: $(CV_CORE_LC)_instr_base_test
description: >
    RISCV-DV generated random interrupt test
plusargs: >
    +instr_cnt=10000
    +num_of_sub_program=20
    +directed_instr_0=riscv_load_store_rand_instr_stream,2
    +directed_instr_1=riscv_mem_region_stress_test,5
    +directed_instr_2=riscv_loop_instr,4
    +directed_instr_3=riscv_hazard_instr_stream,1
    +directed_instr_4=riscv_jal_instr,3
    +directed_instr_5=corev_interrupt_csr_instr_stream,3
    +no_fence=0
    +enable_interrupt=1
    +enable_fast_interrupt_handler=1
    +randomize_csr=1
    +boot_mode=m
    +no_csr_instr=0
