# Test definition YAML for corev-dv test generator

name: corev_rand_instr_obi_err
uvm_test: $(CV_CORE_LC)_instr_base_test
description: >
    RISCV-DV generated random instruction test with OBI instruction bus errors
plusargs: >
    +instr_cnt=10000
    +num_of_sub_program=6
    +directed_instr_0=riscv_load_store_rand_instr_stream,4
    +directed_instr_1=riscv_loop_instr,4
    +directed_instr_2=riscv_hazard_instr_stream,4
    +directed_instr_3=riscv_load_store_hazard_instr_stream,4
    +directed_instr_4=riscv_multi_page_load_store_instr_stream,4
    +directed_instr_5=riscv_mem_region_stress_test,4
    +directed_instr_6=riscv_jal_instr,4
    +directed_instr_7=corev_xori_not_instr,1
    +hint_instr_ratio=2
    +randomize_csr=1
    +boot_mode=m
    +no_csr_instr=0
    +enable_interrupt=1
    +enable_fast_interrupt_handler=1
    +no_wfi=0
    +enable_ebreak_in_debug_rom=0
    +set_dcsr_ebreak=0
    +enable_debug_single_step=1
    +gen_debug_section=1
