//
// Copyright 2020 OpenHW Group
// Copyright 2020 Datum Technology Corporation
// Copyright 2020 Silicon Labs, Inc.
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//

// Libraries
-f ${DV_UVML_HRTBT_PATH}/uvml_hrtbt_pkg.flist
-f ${DV_UVML_TRN_PATH}/uvml_trn_pkg.flist
-f ${DV_UVML_LOGS_PATH}/uvml_logs_pkg.flist
-f ${DV_UVML_SB_PATH}/uvml_sb_pkg.flist
-f ${DV_UVML_MEM_PATH}/uvml_mem_pkg.flist
-f $(DV_SVLIB_PATH)/svlib_pkg.flist

// Agents
-f ${DV_UVMA_CORE_CNTRL_PATH}/uvma_core_cntrl_pkg.flist
-f ${DV_UVMA_OBI_MEMORY_PATH}/src/uvma_obi_memory_pkg.flist
-f ${DV_UVMA_RVFI_PATH}/uvma_rvfi_pkg.flist
-f ${DV_UVMA_RVVI_PATH}/uvma_rvvi_pkg.flist
-f ${DV_UVMA_ISACOV_PATH}/uvma_isacov_pkg.flist
-f ${DV_UVMA_PMA_PATH}/src/uvma_pma_pkg.flist
-f ${DV_UVMA_CLKNRST_PATH}/uvma_clknrst_pkg.flist
-f ${DV_UVMA_INTERRUPT_PATH}/uvma_interrupt_pkg.flist
-f ${DV_UVMA_DEBUG_PATH}/uvma_debug_pkg.flist
-f ${DV_UVMA_RVVI_OVPSIM_PATH}/uvma_rvvi_ovpsim_pkg.flist
-f ${DV_UVMA_FENCEI_PATH}/uvma_fencei_pkg.flist

// Environments
-f ${DV_UVME_PATH}/uvme_cv32e40x_pkg.flist

// CV32E40X test bench Directories
+incdir+${DV_UVMT_PATH}
+incdir+${DV_UVMT_PATH}/../../tests/uvmt
+incdir+${DV_UVMT_PATH}/../../tests/uvmt/base-tests
+incdir+${DV_UVMT_PATH}/../../tests/uvmt/compliance-tests
+incdir+${DV_UVMT_PATH}/../../tests/uvmt/vseq

// CV32E40X tests (includes constants/macros/types meant for test bench)
+incdir+${TBSRC_HOME}
${DV_UVMT_PATH}/uvmt_cv32e40x_pkg.sv

// CV32E40X test bench files
${DV_UVMT_PATH}/uvmt_cv32e40x_dut_wrap.sv
${DV_UVMT_PATH}/uvmt_cv32e40x_tb.sv
${TBSRC_HOME}/core/tb_riscv/include/perturbation_defines.sv
${TBSRC_HOME}/uvmt/uvmt_cv32e40x_tb.sv
${TBSRC_HOME}/uvmt/uvmt_cv32e40x_dut_wrap.sv
${TBSRC_HOME}/core/mm_ram.sv
${TBSRC_HOME}/core/dp_ram.sv
${TBSRC_HOME}/core/tb_riscv/riscv_gnt_stall.sv
${TBSRC_HOME}/core/tb_riscv/riscv_rvalid_stall.sv
${TBSRC_HOME}/core/tb_riscv/riscv_random_interrupt_generator.sv

${DV_UVMT_PATH}/uvmt_cv32e40x_interrupt_assert.sv
${DV_UVMT_PATH}/uvmt_cv32e40x_debug_assert.sv
${DV_UVMT_PATH}/uvmt_cv32e40x_fencei_assert.sv
${DV_UVMT_PATH}/uvmt_cv32e40x_integration_assert.sv
