# Test definition YAML for corev-dv test generator

name: corev_rand_instr_test
uvm_test: $(CV_CORE_LC)_instr_base_test
description: >
    RISCV-DV generated random instruction test
plusargs: >
    +instr_cnt=50000
    +num_of_sub_program=10
    +directed_instr_0=riscv_load_store_rand_instr_stream,4
    +directed_instr_1=riscv_loop_instr,4
    +directed_instr_2=riscv_hazard_instr_stream,4
    +directed_instr_3=riscv_load_store_hazard_instr_stream,4
    +directed_instr_4=riscv_multi_page_load_store_instr_stream,4
    +directed_instr_5=riscv_mem_region_stress_test,4
    +directed_instr_6=riscv_jal_instr,4
    +directed_instr_7=corev_xori_not_instr,1
    +hint_instr_ratio=2
