name: corev_rand_debug_ebreak
uvm_test: $(CV_CORE_LC)_instr_base_test
description: >
    RISCV-DV generated random debug test with ebreak from the debug ROM
plusargs: >
    +instr_cnt=10000
    +num_of_sub_program=0
    +directed_instr_0=riscv_int_numeric_corner_stream,4
    +no_fence=1
    +no_data_page=1
    +no_branch_jump=0
    +boot_mode=m
    +no_csr_instr=0
    +no_wfi=0
    +no_ebreak=0
    +no_dret=1
    +enable_misaligned_instr=1
    +enable_ebreak_in_debug_rom=1
    +set_dcsr_ebreak=1
    +enable_debug_single_step=0
    +gen_debug_section=1
    +num_debug_sub_program=0
    +illegal_instr_ratio=2
    +enable_illegal_csr_instruction=1