variables:
  RISCV: /opt/common/tools/gcc-10.2.0
  RISCV_PREFIX: /shares/common/tools/gcc-10.2.0/bin/riscv-none-elf-
  VERILATOR_ROOT: /opt/common/tools/verilator-4.110
  SPIKE_ROOT: /opt/common/tools/spike
  BBL_ROOT: /opt/common/tools/Linux-ariane-sdk
  SYN_VCS_BASHRC: /opt/synopsys/vcs/XXXX/setup/bashrc.example
  SYN_VERDI_BASHRC: /opt/synopsys/verdi/XXXX/setup/bashrc.ini
  SYN_DCSHELL_BASHRC: /opt/synopsys/syn/XXXX/setup/bashrc
  QUESTA_BASHRC: /opt/questa/XXXX/setup/bashrc
  VIVADO_SETUP: /opt/xilinx/Vivado/XXXX/settings64.sh
  CVA6_REPO: https://github.com/openhwgroup/cva6
  CVA6_BRANCH: master
  COMPLIANCE_REPO: https://github.com/riscv-non-isa/riscv-arch-test.git
  COMPLIANCE_BRANCH: main
  COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437
  COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch
  TESTS_REPO: https://github.com/riscv/riscv-tests.git
  TESTS_BRANCH: master
  TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec
  DV_REPO: https://github.com/google/riscv-dv.git
  DV_BRANCH: master
  NUM_JOBS: 24
  FOUNDRY_PATH: /techno/lib/stdcellXXXX
  TECH_NAME: core_XXXX05v25c
  SYNTH_PERIOD : 30
  LIB_VERILOG: /techno/lib/verilog_XXXX/XXXX.v
  DASHBOARD_USER_EMAIL: user@example.com
  DASHBOARD_USER_NAME: "user"
  DASHBOARD_URL: "git@example.com:namespace/repo_name.git"
  UART_SERIAL: "/dev/ttyUSBXXXX"
  HW_SERVER_URL: "TCP:URLXXX:PORTXXX"
  VIVADO_CMD: "vivado_lab"
  VIVADO2022_SETUP: /opt/common/tools/XXXX/Vivado_Lab/2022.1/settings64.sh
