# YAML file to specify the ci_check regression testlist.
name: cv32e40s_ci_check
description: Commit sanity for the cv32e40s

builds:
  clone_riscv-dv:
    cmd: make clone_riscv-dv
    dir: cv32e40s/sim/uvmt

  clone_svlib:
    cmd: make clone_svlib
    dir: cv32e40s/sim/uvmt

  clone_cv_core_rtl:
    cmd: make clone_cv_core_rtl
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s:
    cmd: make comp_corev-dv comp
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s_pma_1:
    cmd: make comp_corev-dv comp
    cfg: pma_test_cfg_1
    dir: cv32e40s/sim/uvmt

  uvmt_cv32e40s_pma_2:
    cmd: make comp_corev-dv comp
    cfg: pma_test_cfg_2
    dir: cv32e40s/sim/uvmt

tests:
  hello-world:
    build: uvmt_cv32e40s
    description: UVM Hello World Test
    dir: cv32e40s/sim/uvmt
    cmd: make test TEST=hello-world

  interrupt_test:
    build: uvmt_cv32e40s
    description: Interrupt directed test
    dir: cv32e40s/sim/uvmt
    cmd: make test TEST=interrupt_test

  corev_rand_interrupt:
    build: uvmt_cv32e40s
    description: Interrupt random test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_interrupt
    num: 2

  illegal:
    build: uvmt_cv32e40s
    dir: cv32e40s/sim/uvmt
    cmd: make test TEST=illegal

# FIXME: temporarily remove this test from ci_check: see issue #1031.
#  debug_test:
#    build: uvmt_cv32e40s
#    dir: cv32e40s/sim/uvmt
#    cmd: make test TEST=debug_test
#    makearg: USER_RUN_FLAGS=+rand_stall_obi_disable

  csr_instructions:
    build: uvmt_cv32e40s
    description: CSR Instruction Test
    dir: cv32e40s/sim/uvmt
    cmd: make test TEST=csr_instructions

  riscv_arithmetic_basic_test_0:
    build: uvmt_cv32e40s
    description: Static riscv-dv arithmetic test 0
    dir: cv32e40s/sim/uvmt
    cmd: make test TEST=riscv_arithmetic_basic_test_0

  corev_rand_arithmetic_base_test:
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
    description: Generated corev-dv random arithmetic test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test
    num: 1

  corev_rand_instr_test:
    builds:
      - uvmt_cv32e40s
      - uvmt_cv32e40s_pma_1
      - uvmt_cv32e40s_pma_2
    description: Generated corev-dv random instruction test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_instr_test
    num: 1

  corev_rand_jump_stress_test:
    build: uvmt_cv32e40s
    description: Generated corev-dv jump stress test
    dir: cv32e40s/sim/uvmt
    cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test
    num: 2


