diff --git a/Makefile b/Makefile index dde3550f7..50e28a52b 100755 --- a/Makefile +++ b/Makefile @@ -114,7 +114,7 @@ $(library)/.build-srcs: $(ariane_pkg) $(util) $(src) $(library) touch $(library)/.build-srcs # build TBs -$(library)/.build-tb: $(dpi) $(tbs) +$(library)/.build-tb: $(dpi) $(tbs) # Compile top level vlog$(questa_version) -sv $(tbs) -work $(library) touch $(library)/.build-tb @@ -123,11 +123,11 @@ $(library): vlib${questa_version} ${library} # compile DPIs -$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr) +$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr) mkdir -p $(dpi-library) $(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $< -$(dpi-library)/ariane_dpi.so: $(dpi) +$(dpi-library)/ariane_dpi.so: $(dpi) mkdir -p $(dpi-library) # Compile C-code and generate .so file $(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -lfesvr @@ -137,17 +137,17 @@ sim: build vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \ + -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " log -r /*; run -all; exit" \ ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options) -simc: build +simc: build vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ $(QUESTASIM_FLAGS) \ -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " run -all; exit" \ ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options) -$(riscv-asm-tests): build +$(riscv-asm-tests): build vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ $(QUESTASIM_FLAGS) \ @@ -202,7 +202,7 @@ verilate_command := $(verilator) --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc # User Verilator, at some point in the future this will be auto-generated -verilate: +verilate: $(verilate_command) cd $(ver-library) && make -j${NUM_JOBS} -f Variane_testharness.mk @@ -223,10 +223,10 @@ $(addsuffix -verilator,$(riscv-benchmarks)): verilate run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks)) # torture-specific -torture-gen: +torture-gen: cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run' -torture-itest: +torture-itest: cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S' torture-rtest: build @@ -239,14 +239,14 @@ torture-rtest-verilator: verilate cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log make check-torture -run-torture: build +run-torture: build vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \ +BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ $(QUESTASIM_FLAGS) \ -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ ${top_level}_optimized +permissive-off \ - +signature=$(riscv-torture-dir)/output/test.rtlsim.sig ++$(riscv-torture-dir)/output/test ++$(target-options) + +signature=$(riscv-torture-dir)/output/test.rtlsim.sig ++$(riscv-torture-dir)/output/test ++$(target-options) run-torture-verilator: verilate $(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.sig $(riscv-torture-dir)/output/test @@ -257,9 +257,9 @@ check-torture: clean: rm -rf $(riscv-torture-dir)/output/test* - rm -rf $(library)/ $(dpi-library)/ $(ver-library)/ + rm -rf $(library)/ $(dpi-library)/ $(ver-library)/ rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb - + .PHONY: build sim simc verilate clean \ $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \ diff --git a/src/issue_read_operands.sv b/src/issue_read_operands.sv index b6c0949fc..e88de864c 100644 --- a/src/issue_read_operands.sv +++ b/src/issue_read_operands.sv @@ -229,7 +229,7 @@ module issue_read_operands #( // use the zimm as operand a if (issue_instr_i.use_zimm) begin // zero extend operand a - operand_a_n = {52'b0, issue_instr_i.rs1}; + operand_a_n = {52'b0, issue_instr_i.rs1[4:0]}; end // or is it an immediate (including PC), this is not the case for a store and control flow instructions if (issue_instr_i.use_imm && (issue_instr_i.fu != STORE) && (issue_instr_i.fu != CTRL_FLOW)) begin diff --git a/src/util/instruction_trace_item.svh b/src/util/instruction_trace_item.svh index e70d9d064..1a31d900c 100644 --- a/src/util/instruction_trace_item.svh +++ b/src/util/instruction_trace_item.svh @@ -50,17 +50,17 @@ class instruction_trace_item; endfunction // convert register address to ABI compatible form function string regAddrToStr(logic [5:0] addr); - case (addr) + case (addr[4:0]) 0: return "x0"; 1: return "ra"; 2: return "sp"; 3: return "gp"; 4: return "tp"; - 5, 6, 7: return $sformatf("t%0d", (addr - 5)); - 8, 9: return $sformatf("s%0d", (addr - 8)); - 10, 11, 12, 13, 14, 15, 16, 17: return $sformatf("a%0d", (addr - 10)); - 28, 29, 30, 31: return $sformatf("t%0d", (addr - 25)); - default: return $sformatf("s%0d", (addr - 16)); + 5, 6, 7: return $sformatf("t%0d", (addr[4:0] - 5)); + 8, 9: return $sformatf("s%0d", (addr[4:0] - 8)); + 10, 11, 12, 13, 14, 15, 16, 17: return $sformatf("a%0d", (addr[4:0] - 10)); + 28, 29, 30, 31: return $sformatf("t%0d", (addr[4:0] - 25)); + default: return $sformatf("s%0d", (addr[4:0] - 16)); endcase endfunction