diff --git a/docs/02_cva6_requirements/cva6_requirements_specification.rst b/docs/02_cva6_requirements/cva6_requirements_specification.rst
index da5605efb..89fb18de9 100644
--- a/docs/02_cva6_requirements/cva6_requirements_specification.rst
+++ b/docs/02_cva6_requirements/cva6_requirements_specification.rst
@@ -140,15 +140,17 @@ The full list of parameters for this configuration will be detailed in the users
 
 Below are the configuration of the first releases of the CVA6.
 
-+--------------------+---------+---------+------+-------+---------+---------+---------+---------+
-| Release ID         | Target  | ISA     | XLEN | FPU   | CV-X-IF | MMU     | L1 D$   | L1 I$   |
-+====================+=========+=========+======+=======+=========+=========+=========+=========+
-| ``CV32A60X``       | ASIC    | IMC     |  32  | No    | Yes     | None    | 2 kB    | 2 kB    |
-+--------------------+---------+---------+------+-------+---------+---------+---------+---------+
-| ``CV32A60AX``      | ASIC    | IMC     |  32  | No    | Yes     | Sv32    | 16kB    | 16 kB   |
-+--------------------+---------+---------+------+-------+---------+---------+---------+---------+
++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+
+| Release ID         | Target  | ISA (main ext.) | XLEN | FPU   | CV-X-IF | MMU     | L1 D$   | L1 I$   |
++====================+=========+=================+======+=======+=========+=========+=========+=========+
+| ``CV32A60X``       | ASIC    | IMC             |  32  | No    | Yes     | None    | (2 kB)  | (2 kB)  |
++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+
+| ``CV32A60AX``      | ASIC    | IMC             |  32  | No    | Yes     | Sv32    | 16kB    | 16 kB   |
++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+
+| ``CV64A60AX``      | ASIC    | IMACFDB         |  64  | Yes   | Yes     | Sv39    | 32kB    | 32 kB   |
++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+
 
-CV32A60X could evolve to CV32A65X if the team decides to integrate the dual-issue optional architectural feature.
+Note for CV32A60X: Its first industrial use is without caches. Therefore its cache size is not representative.
 
 .. Possible Future Releases
 .. ------------------------
@@ -311,8 +313,8 @@ independent requirements.
 +-----------------------------------+-----------------------------------+
 | ISA-130                           | CVA6 should support as an         |
 |                                   | **option** the **Zicond**         |
-|                                   | extension(ratification pending)   |
-|                                   | version 1.0.                      |
+|                                   | extension (integer conditional    |
+|                                   | operations) version 1.0.          |
 +-----------------------------------+-----------------------------------+
 | ISA-140                           | CVA6 should support as an         |
 |                                   | **option** the **Zcb**            |
@@ -322,9 +324,20 @@ independent requirements.
 |                                   | **option** the **Zcmp**           |
 |                                   | extension version 1.0.            |
 +-----------------------------------+-----------------------------------+
+| ISA-160                           | CVA6 should support as an         |
+|                                   | **option** the **Zcmt**           |
+|                                   | extension version 1.0.            |
++-----------------------------------+-----------------------------------+
+| ISA-170                           | CVA6 should support as an         |
+|                                   | **option** the **Zkn** extension  |
+|                                   | (NIST algorithm suite). The       |
+|                                   | **Zkn** extension comprises the   |
+|                                   | **Zbkb**, **Zbkc**, **Zbkx**,     |
+|                                   | **Zkne**, **Zknd** and **Zknh**   |
+|                                   | extensions.                       |
++-----------------------------------+-----------------------------------+
 
-
-Note to ISA-60 and ISA-70: CV64A6 cannot support the D extension with
+Note to ISA-60 and ISA-70: CV64A6 cannot support the D extension without
 the F extension.
 
 .. _privileges_and_virtual_memory:
@@ -545,6 +558,11 @@ size/ways configurations may be implemented in the design.
 
 The design will support one replacement policy allowed by L1W-80.
 
+These L1WTD requirements apply to the legacy WT cache from PULP.
+They also apply to the HPDCache that will supersede the legacy PULP caches.
+Note that the HPDCache has more features, such as write-back options, that
+are beyond the scope of this specification.
+
 .. _l1_instruction_cache:
 
 L1 Instruction cache
@@ -650,8 +668,16 @@ integrated in the continuous integration flow.
 | PPA‑10                            | CVA6 should be resource-optimized |
 |                                   | on FPGA and ASIC targets.         |
 +-----------------------------------+-----------------------------------+
-| PPA‑20                            | CVA6 should deliver more than 2.1 |
-|                                   | CoreMark/MHz.                     |
+| PPA‑20                            | CVA6 should target 3.0            |
+|                                   | CoreMark/MHz , assuming a         |
+|                                   | sufficiently fast memory          |
+|                                   | hierarchy.                        |
++-----------------------------------+-----------------------------------+
+| PPA‑25                            | CVA6 should target as an          |
+|                                   | **option** 4.5                    |
+|                                   | CoreMark/MHz, assuming a          |
+|                                   | sufficiently fast memory          |
+|                                   | hierarchy.                        |
 +-----------------------------------+-----------------------------------+
 | PPA‑30                            | CV32A6 should run at more than    |
 |                                   | 150 MHz in the cv32a6_imac_sv32   |
@@ -675,6 +701,8 @@ integrated in the continuous integration flow.
 |                                   | performance per MHz.              |
 +-----------------------------------+-----------------------------------+
 
+PPA-25 comes with the optional dual-issue feature.
+
 .. _interface_requirements:
 
 Interface requirements
@@ -785,6 +813,10 @@ integration in FPGA and ASIC design flows:
 | RUL‑40                            | CVA6 should not include           |
 |                                   | technology-dependent blocks.      |
 +-----------------------------------+-----------------------------------+
+| RUL-50                            | CVA6 should support as an         |
+|                                   | **option** protection of SRAM     |
+|                                   | against single-event upsets (SEU).|
++-----------------------------------+-----------------------------------+
 
 If technology-dependent blocks are used, e.g. to improve PPA on certain
 targets, the equivalent technology-independent block should be