diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 1b8421a25..38a1d642a 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -6,7 +6,7 @@ testALU:
   stage: test
   script:
     - make build
-    - vsim-10.5c alu_tb_optimized -c +UVM_TESTNAME=alu_test -coverage -do "coverage save -onexit alu.ucdb; run -a; exit"
+    - make alu
     - vcover report alu.ucdb
     - vcover report -html alu.ucdb
   artifacts:
diff --git a/Makefile b/Makefile
index cd0b3e5e3..2ee77ec6d 100644
--- a/Makefile
+++ b/Makefile
@@ -5,14 +5,20 @@
 # compile everything in the following library
 library = work
 # Top level module to compile
-top_level = alu_tb
+top_level = ariane
+test_top_level = alu_tb
+tests = alu scoreboard
 # path to agents
 agents = tb/agents/fu_if/fu_if.sv tb/agents/fu_if/fu_if_agent_pkg.sv \
 	include/ariane_pkg.svh tb/agents/scoreboard_if/scoreboard_if.sv tb/agents/scoreboard_if/scoreboard_if_agent_pkg.sv
 
+interfaces = include/debug_if.svh include/mem_if.svh
 # this list contains the standalone components
 src = alu.sv tb/sequences/alu_sequence_pkg.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv tb/alu_tb.sv \
-	  issue_read_operands.sv decoder.sv
+	  tb/scoreboard_tb.sv \
+	  if_stage.sv compressed_decoder.sv fetch_fifo.sv commit_stage.sv prefetch_buffer.sv \
+	  scoreboard.sv issue_read_operands.sv decoder.sv id_stage.sv util/cluster_clock_gating.sv regfile.sv ex_stage.sv ariane.sv \
+	  tb/core_tb.sv
 
 # Search here for include files (e.g.: non-standalone components)
 incdir = ./includes
@@ -29,21 +35,26 @@ list_incdir = $(foreach dir, ${incdir}, +incdir+$(dir))
 # Build the TB and module using QuestaSim
 build:
 	# Create the library
-#	rm -rf ${library}
 	vlib${questa_version} ${library}
 	# Suppress message that always_latch may not be checked thoroughly bu Questa.
 	# Compile agents
 	vlog${questa_version} ${compile_flag} -incr ${agents} ${list_incdir} -suppress 2583
+	# Compile interfaces
+	vlog${questa_version} ${compile_flag} -incr ${interfaces} ${list_incdir} -suppress 2583
 	# Compile source files
 	vlog${questa_version} ${compile_flag} -incr ${src} ${list_incdir} -suppress 2583
 	# Optimize top level
-	vopt${questa_version} ${compile_flag} ${top_level} -o ${top_level}_optimized +acc -check_synthesis
+	vopt${questa_version} ${compile_flag} ${test_top_level} -o ${test_top_level}_optimized +acc -check_synthesis
 
 # Run the specified test case
 sim:
 	# vsim${questa_version} ${top_level}_optimized -c -do "run -a"
 	vsim${questa_version} ${top_level}_optimized +UVM_TESTNAME=${test_case} -do "run -a"
 
+$(tests):
+	# Optimize top level
+	vopt${questa_version} ${compile_flag} $@_tb -o $@_optimized +acc -check_synthesis
+	vsim${questa_version} -c +UVM_TESTNAME=$@_test -coverage -do "coverage save -onexit $@.ucdb; run -a; exit" $@_tb_optimized
 # User Verilator to lint the target
 lint:
 	verilator ${src} --lint-only \
@@ -51,5 +62,6 @@ lint:
 
 clean:
 	rm -rf work/
+
 .PHONY:
 	build lint
diff --git a/include/mem_if.svh b/include/mem_if.svh
index 3d192ddac..56f52038d 100644
--- a/include/mem_if.svh
+++ b/include/mem_if.svh
@@ -31,8 +31,8 @@ interface mem_if
         // Memory interface configured as slave
         modport Slave
         (
-            input   address, data_wdata, data_req, data_we, data_be,
-            output  data_gnt, data_rvalid, data_rdata
+            output  address, data_wdata, data_req, data_we, data_be,
+            input   data_gnt, data_rvalid, data_rdata
         );
 endinterface
 `endif
\ No newline at end of file
diff --git a/tb/agents/scoreboard_if/scoreboard_if.sv b/tb/agents/scoreboard_if/scoreboard_if.sv
index 8f2eaf252..473dc376d 100644
--- a/tb/agents/scoreboard_if/scoreboard_if.sv
+++ b/tb/agents/scoreboard_if/scoreboard_if.sv
@@ -29,19 +29,19 @@ interface scoreboard_if (input clk);
     scoreboard_entry                       issue_instr;
     wire                                   issue_instr_valid;
     wire                                   issue_ack;
-    wire [63:0]                            pc;
+    wire [4:0]                             trans_id;
     wire [63:0]                            wdata;
     wire                                   wb_valid;
 
     // Scoreboard interface configured as master
     clocking mck @(posedge clk);
         default input #1 output #5; // save timing
-        output   flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, pc, wdata, wb_valid;
+        output   flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, trans_id, wdata, wb_valid;
         input    full, rd_clobber, rs1, rs1_valid, rs2, rs2_valid, commit_instr, issue_instr, issue_instr_valid;
     endclocking
     // Scoreboard interface configured in passive mode (-> monitor)
     clocking pck @(posedge clk);
-        input flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, pc, wdata, wb_valid,
+        input flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, trans_id, wdata, wb_valid,
               full, rd_clobber, rs1, rs1_valid, rs2, rs2_valid, commit_instr, issue_instr, issue_instr_valid;
     endclocking
 
diff --git a/tb/core_tb.sv b/tb/core_tb.sv
new file mode 100755
index 000000000..138c939fc
--- /dev/null
+++ b/tb/core_tb.sv
@@ -0,0 +1,71 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 15/04/2017
+// Description: Top level testbench module. Instantiates the top level DUT, configures
+//              the virtual interfaces and starts the test passed by +UVM_TEST+
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+
+import ariane_pkg::*;
+
+module core_tb;
+
+
+    logic clk_i;
+    logic rst_ni;
+    logic clock_en_i;
+    logic test_en_i;
+    logic fetch_enable_i;
+    logic core_busy_o;
+    logic [-1:0] ext_perf_counters_i;
+    logic [63:0] boot_addr_i;
+    logic [3:0] core_id_i;
+    logic [5:0] cluster_id_i;
+    mem_if instr_if();
+    mem_if data_if();
+    logic irq_i;
+    logic [4:0] irq_id_i;
+    logic irq_ack_o;
+    logic irq_sec_i;
+    logic sec_lvl_o;
+    debug_if debug_if();
+
+    ariane i_ariane (
+        .clk_i              (clk_i              ),
+        .rst_n              (rst_ni             ),
+        .clock_en_i         (clock_en_i         ),
+        .test_en_i          (test_en_i          ),
+        .fetch_enable_i     (fetch_enable_i     ),
+        .core_busy_o        (core_busy_o        ),
+        .ext_perf_counters_i(ext_perf_counters_i),
+        .boot_addr_i        (boot_addr_i        ),
+        .core_id_i          (core_id_i          ),
+        .cluster_id_i       (cluster_id_i       ),
+        .instr_if           (instr_if           ),
+        .data_if            (data_if            ),
+        .irq_i              (irq_i              ),
+        .irq_id_i           (irq_id_i           ),
+        .irq_ack_o          (irq_ack_o          ),
+        .irq_sec_i          (irq_sec_i          ),
+        .sec_lvl_o          (sec_lvl_o          ),
+        .debug_if           (debug_if           )
+    );
+
+    // clock process
+    initial begin
+        clk_i = 1'b0;
+        rst_ni = 1'b0;
+        repeat(8)
+            #10ns clk_i = ~clk_i;
+
+        rst_ni = 1'b1;
+        forever
+            #10ns clk_i = ~clk_i;
+    end
+
+    program testbench (mem_if instr_if);
+
+    endprogram
+
+    testbench tb(instr_if);
+endmodule
\ No newline at end of file
diff --git a/tb/models/scoreboard.sv b/tb/models/scoreboard.sv
index e1352ae1f..42503d298 100755
--- a/tb/models/scoreboard.sv
+++ b/tb/models/scoreboard.sv
@@ -6,9 +6,9 @@ class Scoreboard;
 
     // utility function to get randomized input data
     static function automatic scoreboard_entry randomize_scoreboard();
-            exception exception = { 64'h55, 63'h0, 1'b0};
+            exception exception = { pc, 63'h0, 1'b0};
             scoreboard_entry entry = {
-                pc, ALU, ADD, 5'h5, 5'h5, 5'h5, 64'h0, 1'b0, 1'b0, exception
+                ALU, ADD, 5'h5, 5'h5, 5'h5, 64'h0, 1'b0, 1'b0, exception
             };
             pc++;
             return entry;
@@ -27,9 +27,9 @@ class Scoreboard;
     endfunction : get_issue
 
     // write back to scoreboard
-    function void write_back(logic [63:0] pc, logic [63:0] value);
+    function void write_back(logic [4:0] trans_id, logic [63:0] value);
         for (int i = 0; i < $size(issued_instructions); i++) begin
-            if (issued_instructions[i].pc == pc) begin
+            if (issued_instructions[i].trans_id == trans_id) begin
                 issued_instructions[i].valid = 1'b1;
                 issued_instructions[i].result  = value;
             end
diff --git a/tb/scoreboard_tb.sv b/tb/scoreboard_tb.sv
index 609321f8c..b6a1968ae 100755
--- a/tb/scoreboard_tb.sv
+++ b/tb/scoreboard_tb.sv
@@ -37,7 +37,7 @@ module scoreboard_tb;
         .issue_instr_o        ( scoreboard_if.issue_instr         ),
         .issue_instr_valid_o  ( scoreboard_if.issue_instr_valid   ),
         .issue_ack_i          ( scoreboard_if.issue_ack           ),
-        .pc_i                 ( scoreboard_if.pc                  ),
+        .trans_id_i           ( scoreboard_if.trans_id            ),
         .wdata_i              ( scoreboard_if.wdata               ),
         .wb_valid_i           ( scoreboard_if.wb_valid            )
     );
@@ -107,10 +107,10 @@ module scoreboard_tb;
                             repeat ($urandom_range(1,20)) @(scoreboard_if.mck);
                             wb_lock.get(1);
                             // $display("Time: %t, Writing Back: %0h", $time, thread_copy.pc);
-                            scoreboard_if.mck.pc <= thread_copy.pc;
+                            scoreboard_if.mck.trans_id <= thread_copy.trans_id;
                             scoreboard_if.mck.wdata <= rand_data;
                             scoreboard_if.mck.wb_valid <= 1'b1;
-                            sb.write_back(thread_copy.pc, rand_data);
+                            sb.write_back(thread_copy.trans_id, rand_data);
                             @(scoreboard_if.mck);
                             scoreboard_if.mck.wb_valid <= 1'b0;
                             wb_lock.put(1);
@@ -158,7 +158,7 @@ module scoreboard_tb;
                 @(scoreboard_if.pck);
                 if (scoreboard_if.pck.issue_instr_valid == 1'b1 && scoreboard_if.pck.issue_ack) begin
                     tmp_sbe = sb.get_issue();
-                    assert (tmp_sbe.pc == issue_instruction.pc) else $error("Issue instruction mismatch. Expected: %0h Got: %0h", tmp_sbe, issue_instruction);
+                    assert (tmp_sbe.trans_id == issue_instruction.trans_id) else $error("Issue instruction mismatch. Expected: %0h Got: %0h", tmp_sbe, issue_instruction);
                 end
             end
         end