From 059b17738245d33a82fc6f46a446cea2ac6aaa24 Mon Sep 17 00:00:00 2001
From: Florian Zaruba <fl.zaruba@be4web.net>
Date: Mon, 5 Jun 2017 18:54:59 +0200
Subject: [PATCH] Add submodule init to .gitlab-ci.yml

---
 .gitlab-ci.yml     | 1 +
 src/csr_regfile.sv | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 22e54def7..b948473c8 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -71,6 +71,7 @@ test_store_queue:
 test_core:
   stage: test
   before_script:
+    - git submodule update --init --recursive
     - make build-tests
     - make build library=core_lib
   script:
diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv
index 94b73f44c..105789bfe 100644
--- a/src/csr_regfile.sv
+++ b/src/csr_regfile.sv
@@ -375,7 +375,7 @@ module csr_regfile #(
         // throw an illegal instruction exception
         if (update_access_exception || read_access_exception) begin
             csr_exception_o = {
-                pc_i, ILLEGAL_INSTR, 1'b1
+                ILLEGAL_INSTR, pc_i, 1'b1 // TODO: Instead of PC the instruction bits should be here
             };
         end
     end