diff --git a/Makefile b/Makefile index 2ee77ec6d..903bda702 100644 --- a/Makefile +++ b/Makefile @@ -5,8 +5,8 @@ # compile everything in the following library library = work # Top level module to compile -top_level = ariane -test_top_level = alu_tb +top_level = core_tb +test_top_level = core_tb tests = alu scoreboard # path to agents agents = tb/agents/fu_if/fu_if.sv tb/agents/fu_if/fu_if_agent_pkg.sv \ @@ -49,7 +49,7 @@ build: # Run the specified test case sim: # vsim${questa_version} ${top_level}_optimized -c -do "run -a" - vsim${questa_version} ${top_level}_optimized +UVM_TESTNAME=${test_case} -do "run -a" + vsim${questa_version} ${top_level}_optimized +UVM_TESTNAME=${test_case} $(tests): # Optimize top level diff --git a/alu.sv b/alu.sv index d44a16402..8916eabb9 100644 --- a/alu.sv +++ b/alu.sv @@ -20,11 +20,6 @@ module alu input logic [63:0] operand_a_i, input logic [63:0] operand_b_i, - input logic [64:0] multdiv_operand_a_i, - input logic [64:0] multdiv_operand_b_i, - - input logic multdiv_en_i, - output logic [63:0] adder_result_o, output logic [65:0] adder_result_ext_o, @@ -75,11 +70,11 @@ module alu end // prepare operand a - assign adder_in_a = multdiv_en_i ? multdiv_operand_a_i : {operand_a_i, 1'b1}; + assign adder_in_a = {operand_a_i, 1'b1}; // prepare operand b assign operand_b_neg = {operand_b_i, 1'b0} ^ {65{adder_op_b_negate}}; - assign adder_in_b = multdiv_en_i ? multdiv_operand_b_i : operand_b_neg ; + assign adder_in_b = operand_b_neg ; // actual adder assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b); diff --git a/ariane.sv b/ariane.sv index 58b6bfe30..3c080584f 100644 --- a/ariane.sv +++ b/ariane.sv @@ -45,7 +45,6 @@ module ariane ); - logic rst_ni; logic flush_i; // logic [31:0] instruction_i; // logic instruction_valid_i; @@ -68,7 +67,6 @@ module ariane // synth stuff assign flush_i = 1'b0; - logic req_i; logic if_busy_o; logic id_ready_i; logic halt_if_i; @@ -90,27 +88,32 @@ module ariane logic mult_valid_i; priv_lvl_t priv_lvl_o; exception exception_o; + scoreboard_entry commit_instr_o; -if_stage i_if_stage ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .req_i ( req_i ), - .if_busy_o ( if_busy_o ), - .id_ready_i ( id_ready_i ), - .halt_if_i ( halt_if_i ), - .instr_req_o ( instr_if.data_req ), - .instr_addr_o ( instr_if.address ), - .instr_gnt_i ( instr_if.data_gnt ), - .instr_rvalid_i ( instr_if.data_rvalid ), - .instr_rdata_i ( instr_if.data_rdata ), - .instr_valid_id_o ( instr_valid_id_o ), - .instr_rdata_id_o ( instr_rdata_id_o ), - .is_compressed_id_o ( is_compressed_id_o ), - .illegal_c_insn_id_o ( illegal_c_insn_id_o ), - .pc_if_o ( pc_if_o ), - .pc_id_o ( pc_id_o ), - .boot_addr_i ( boot_addr_i ) -); + assign id_ready_i = 1'b1; + assign halt_if_i = 1'b0; + + if_stage i_if_stage ( + .clk_i ( clk_i ), + .rst_ni ( rst_n ), + .flush_i ( 1'b0 ), + .req_i ( fetch_enable_i ), + .if_busy_o ( if_busy_o ), + .id_ready_i ( id_ready_i ), + .halt_if_i ( halt_if_i ), + .instr_req_o ( instr_if.data_req ), + .instr_addr_o ( instr_if.address ), + .instr_gnt_i ( instr_if.data_gnt ), + .instr_rvalid_i ( instr_if.data_rvalid ), + .instr_rdata_i ( instr_if.data_rdata ), + .instr_valid_id_o ( instr_valid_id_o ), + .instr_rdata_id_o ( instr_rdata_id_o ), + .is_compressed_id_o ( is_compressed_id_o ), + .illegal_c_insn_id_o ( illegal_c_insn_id_o ), + .pc_if_o ( pc_if_o ), + .pc_id_o ( pc_id_o ), + .boot_addr_i ( boot_addr_i ) + ); id_stage #( @@ -118,13 +121,13 @@ if_stage i_if_stage ( ) id_stage_i ( .clk_i ( clk_i ), - .rst_ni ( rst_ni ), + .rst_ni ( rst_n ), .test_en_i ( test_en_i ), .flush_i ( flush_i ), .instruction_i ( instr_rdata_id_o ), .instruction_valid_i ( instr_valid_id_o ), .pc_if_i ( pc_if_o ), // PC from if - .ex_i ( ), // exception from if + .ex_i ( '{default: 0} ), // exception from if .ready_o ( ready_o ), .operator_o ( operator_o ), .operand_a_o ( operand_a_o ), @@ -150,7 +153,7 @@ if_stage i_if_stage ( ex_stage ex_stage_i ( .clk_i ( clk_i ), - .rst_ni ( rst_ni ), + .rst_ni ( rst_n ), .operator_i ( operator_o ), .operand_a_i ( operand_a_o ), .operand_b_i ( operand_b_o ), @@ -171,7 +174,7 @@ if_stage i_if_stage ( commit_stage i_commit_stage ( .clk_i ( clk_i ), - .rst_ni ( rst_ni ), + .rst_ni ( rst_n ), .priv_lvl_o ( priv_lvl_o ), .exception_o ( exception_o ), .commit_instr_i ( commit_instr_o ), diff --git a/commit_stage.sv b/commit_stage.sv index 3d0373503..513ccc7fa 100644 --- a/commit_stage.sv +++ b/commit_stage.sv @@ -33,7 +33,8 @@ module commit_stage ( // commit instruction always_comb begin : commit // default assignments - we_a_o = 1'b0; + commit_ack_o = 1'b0; + we_a_o = 1'b0; if (commit_instr_i.valid) begin we_a_o = 1'b1; commit_ack_o = 1'b1; diff --git a/decoder.sv b/decoder.sv index 9530483cc..65e4c30e3 100644 --- a/decoder.sv +++ b/decoder.sv @@ -82,15 +82,24 @@ module decoder ( end OPCODE_OP32: begin - + instruction_o.fu = ALU; + instruction_o.rs1 = instr.rtype.rs1; + instruction_o.rs2 = instr.rtype.rs2; + instruction_o.rd = instr.rtype.rd; end OPCODE_OPIMM: begin + instruction_o.fu = ALU; imm_select = IIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; end OPCODE_OPIMM32: begin + instruction_o.fu = ALU; imm_select = IIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; end OPCODE_STORE: begin diff --git a/ex_stage.sv b/ex_stage.sv index e6c32153c..12776ad7e 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -25,8 +25,8 @@ module ex_stage ( ); -// ALU is a single cycle instructions -assign alu_ready_o = alu_valid_i; +// ALU is a single cycle instructions, hence it is always ready +assign alu_ready_o = 1'b1; assign alu_valid_o = alu_valid_i; assign alu_trans_id_o = trans_id_i; @@ -34,9 +34,6 @@ alu alu_i ( .operator_i ( operator_i ), .operand_a_i ( operand_a_i ), .operand_b_i ( operand_b_i ), - .multdiv_operand_a_i ( ), - .multdiv_operand_b_i ( ), - .multdiv_en_i ( ), .adder_result_o ( ), .adder_result_ext_o ( ), .result_o ( alu_result_o ), diff --git a/id_stage.sv b/id_stage.sv index 7f7161a77..4d6dc1077 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -68,7 +68,7 @@ module id_stage #( // TODO: Branching logic assign ready_o = ~full_o; - logic illegal_instr_o; + logic illegal_instr_o; decoder decoder_i ( .clk_i ( clk_i ), diff --git a/if_stage.sv b/if_stage.sv index 0e8547475..16ab2d890 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -31,6 +31,7 @@ import ariane_pkg::*; module if_stage ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low + input logic flush_i, input logic req_i, // request new instructions output logic if_busy_o, // is the IF stage busy fetching instructions? input logic id_ready_i, @@ -65,19 +66,20 @@ module if_stage ( // offset FSM enum logic[0:0] {WAIT, IDLE} offset_fsm_cs, offset_fsm_ns; - - assign pc_if_o = fetch_addr; - - // compressed instruction decoding, or more precisely compressed instruction - // expander - // - // since it does not matter where we decompress instructions, we do it here - // to ease timing closure logic [31:0] instr_decompressed; logic illegal_c_insn; logic instr_compressed_int; logic clear_instr_valid_i; + + assign pc_if_o = fetch_addr; + // id stage acknowledged + assign clear_instr_valid_i = id_ready_i; + // compressed instruction decoding, or more precisely compressed instruction + // expander + // + // since it does not matter where we decompress instructions, we do it here + // to ease timing closure compressed_decoder compressed_decoder_i ( .instr_i ( fetch_rdata ), @@ -94,7 +96,7 @@ module if_stage ( .req_i ( req_i ), - .branch_i ( ), // kill everything + .branch_i ( flush_i ), // kill everything .addr_i ( {fetch_addr_n[63:1], 1'b0} ), .ready_i ( fetch_ready ), @@ -113,7 +115,7 @@ module if_stage ( .busy_o ( prefetch_busy ) ); - assign fetch_addr_n = {boot_addr_i[63:8], EXC_OFF_RST}; + assign fetch_addr_n = 64'b0; //{boot_addr_i[63:8], EXC_OFF_RST}; // offset FSM state always_ff @(posedge clk_i, negedge rst_ni) @@ -202,7 +204,7 @@ module if_stage ( assign if_ready = valid & id_ready_i; - assign if_valid = (~halt_if_i) & id_ready_i; + assign if_valid = (~halt_if_i) & if_ready; assign if_busy_o = prefetch_busy; //------------- // Assertions diff --git a/include/ariane_pkg.svh b/include/ariane_pkg.svh index ed4519807..24986d51d 100644 --- a/include/ariane_pkg.svh +++ b/include/ariane_pkg.svh @@ -80,35 +80,35 @@ package ariane_pkg; // Instruction Types // -------------------- typedef struct packed { - logic [6:0] opcode; - logic [11:7] rd; - logic [14:12] funct3; - logic [19:15] rs1; - logic [24:20] rs2; logic [31:25] funct7; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] rd; + logic [6:0] opcode; } rtype; typedef struct packed { - logic [6:0] opcode; - logic [11:7] rd; - logic [14:12] funct3; - logic [19:15] rs1; logic [31:20] imm; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] rd; + logic [6:0] opcode; } itype; typedef struct packed { - logic [6:0] opcode; - logic [11:7] imm0; - logic [14:12] funct3; - logic [19:15] rs1; - logic [24:20] rs2; logic [31:25] imm1; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] imm0; + logic [6:0] opcode; } stype; typedef struct packed { - logic [6:0] opcode; - logic [11:7] rd; logic [31:12] funct3; + logic [11:7] rd; + logic [6:0] opcode; } utype; typedef union packed { diff --git a/include/mem_if.svh b/include/mem_if.svh index 56f52038d..8b50faa84 100644 --- a/include/mem_if.svh +++ b/include/mem_if.svh @@ -9,30 +9,47 @@ // Guard statement proposed by "Easier UVM" (doulos) `ifndef MEM_IF__SV `define MEM_IF__SV -interface mem_if - #( - parameter int ADDRESS_SIZE = 64 - ); - logic [ADDRESS_SIZE-1:0] address; // Address for read/write request - logic [31:0] data_wdata; // Data to be written - logic data_req; // Requests read data - logic data_gnt; // Request has been granted, signals can be changed as - // soon as request has been granted - logic data_rvalid; // Read data is valid - logic [31:0] data_rdata; // Read data - logic data_we; // Write enable - logic [3:0] data_be; // Byte enable +interface mem_if #(parameter int ADDRESS_SIZE = 64, + parameter int DATA_WIDTH = 64 ) + (input clk); + wire [ADDRESS_SIZE-1:0] address; // Address for read/write request + wire [DATA_WIDTH-1:0] data_wdata; // Data to be written + wire data_req; // Requests read data + wire data_gnt; // Request has been granted, signals can be changed as + // soon as request has been granted + wire data_rvalid; // Read data is valid + wire [DATA_WIDTH-1:0] data_rdata; // Read data + wire data_we; // Write enable + wire [DATA_WIDTH/8-1:0] data_be; // Byte enable // Memory interface configured as master - modport Master - ( + clocking mck @(posedge clk); + default input #1ns output #1ns; + input address, data_wdata, data_req, data_we, data_be; + output data_gnt, data_rvalid, data_rdata; + endclocking + // Memory interface configured as slave + clocking sck @(posedge clk); + default input #1ns output #1ns; + output address, data_wdata, data_req, data_we, data_be; + input data_gnt, data_rvalid, data_rdata; + endclocking + + clocking pck @(posedge clk); + default input #1ns output #1ns; + input address, data_wdata, data_req, data_we, data_be, + data_gnt, data_rvalid, data_rdata; + endclocking + + modport Master ( + clocking mck, input address, data_wdata, data_req, data_we, data_be, output data_gnt, data_rvalid, data_rdata ); - // Memory interface configured as slave - modport Slave - ( + modport Slave ( + clocking sck, output address, data_wdata, data_req, data_we, data_be, input data_gnt, data_rvalid, data_rdata ); + // modport Passive (clocking pck); endinterface `endif \ No newline at end of file diff --git a/issue_read_operands.sv b/issue_read_operands.sv index 5561bc866..2d49fd21b 100755 --- a/issue_read_operands.sv +++ b/issue_read_operands.sv @@ -57,6 +57,7 @@ module issue_read_operands ( // output flipflop (ID <-> EX) logic [63:0] operand_a_n, operand_a_q, operand_b_n, operand_b_q; logic alu_valid_n, alu_valid_q; + logic [4:0] trans_id_n, trans_id_q; alu_op operator_n, operator_q; // forwarding signals @@ -66,6 +67,7 @@ module issue_read_operands ( assign operand_b_o = operand_b_q; assign operator_o = operator_q; assign alu_valid_o = alu_valid_q; + assign trans_id_o = trans_id_q; // --------------- // Issue Stage // --------------- @@ -158,15 +160,17 @@ module issue_read_operands ( operand_b_n = issue_instr_i.imm; end + trans_id_n = issue_instr_i.trans_id; + operator_n = issue_instr_i.op; end // FU select always_comb begin : unit_valid - alu_valid_n = alu_valid_q; + alu_valid_n = 1'b0; lsu_valid_o = 1'b0; mult_valid_o = 1'b0; // Exception pass through // if an exception has occurred simply pass it through - if (~issue_instr_i.ex.valid) begin + if (~issue_instr_i.ex.valid && issue_instr_valid_i) begin case (issue_instr_i.fu) ALU: alu_valid_n = 1'b1; @@ -208,11 +212,13 @@ module issue_read_operands ( operand_b_q <= '{default: 0}; alu_valid_q <= 1'b0; operator_q <= ADD; + trans_id_q <= 5'b0; end else begin operand_a_q <= operand_a_n; operand_b_q <= operand_b_n; alu_valid_q <= alu_valid_n; operator_q <= operator_n; + trans_id_q <= trans_id_n; end end endmodule diff --git a/scoreboard.sv b/scoreboard.sv index 3e5416932..8c4bab720 100644 --- a/scoreboard.sv +++ b/scoreboard.sv @@ -179,8 +179,9 @@ always_comb begin : issue_instruction // provide a combinatorial path in case the scoreboard is empty if (top_pointer_q == issue_pointer_q) begin - issue_instr_o = decoded_instr_i; - issue_instr_valid_o = decoded_instr_valid_i; + issue_instr_o = decoded_instr_i; + issue_instr_o.trans_id = issue_pointer_q; + issue_instr_valid_o = decoded_instr_valid_i; // if not empty go to scoreboard and get the instruction at the issue pointer end else begin issue_instr_o = mem_q[$unsigned(issue_pointer_q)]; diff --git a/tb/core_tb.sv b/tb/core_tb.sv index 138c939fc..001832d3a 100755 --- a/tb/core_tb.sv +++ b/tb/core_tb.sv @@ -17,12 +17,11 @@ module core_tb; logic test_en_i; logic fetch_enable_i; logic core_busy_o; - logic [-1:0] ext_perf_counters_i; logic [63:0] boot_addr_i; logic [3:0] core_id_i; logic [5:0] cluster_id_i; - mem_if instr_if(); - mem_if data_if(); + mem_if #(.DATA_WIDTH(32)) instr_if(clk_i); + mem_if data_if(clk_i); logic irq_i; logic [4:0] irq_id_i; logic irq_ack_o; @@ -30,25 +29,28 @@ module core_tb; logic sec_lvl_o; debug_if debug_if(); - ariane i_ariane ( - .clk_i (clk_i ), - .rst_n (rst_ni ), - .clock_en_i (clock_en_i ), - .test_en_i (test_en_i ), - .fetch_enable_i (fetch_enable_i ), - .core_busy_o (core_busy_o ), - .ext_perf_counters_i(ext_perf_counters_i), - .boot_addr_i (boot_addr_i ), - .core_id_i (core_id_i ), - .cluster_id_i (cluster_id_i ), - .instr_if (instr_if ), - .data_if (data_if ), - .irq_i (irq_i ), - .irq_id_i (irq_id_i ), - .irq_ack_o (irq_ack_o ), - .irq_sec_i (irq_sec_i ), - .sec_lvl_o (sec_lvl_o ), - .debug_if (debug_if ) + assign boot_addr_i = 64'b0; + assign test_en_i = 1'b0; + + ariane dut ( + .clk_i ( clk_i ), + .rst_n ( rst_ni ), + .clock_en_i ( clock_en_i ), + .test_en_i ( test_en_i ), + .fetch_enable_i ( fetch_enable_i ), + .core_busy_o ( core_busy_o ), + .ext_perf_counters_i ( ), + .boot_addr_i ( boot_addr_i ), + .core_id_i ( core_id_i ), + .cluster_id_i ( cluster_id_i ), + .instr_if ( instr_if ), + .data_if ( data_if ), + .irq_i ( irq_i ), + .irq_id_i ( irq_id_i ), + .irq_ack_o ( irq_ack_o ), + .irq_sec_i ( irq_sec_i ), + .sec_lvl_o ( sec_lvl_o ), + .debug_if ( debug_if ) ); // clock process @@ -57,14 +59,48 @@ module core_tb; rst_ni = 1'b0; repeat(8) #10ns clk_i = ~clk_i; - rst_ni = 1'b1; forever #10ns clk_i = ~clk_i; end - program testbench (mem_if instr_if); + initial begin + fetch_enable_i = 1'b0; + wait(rst_ni) + #1ns fetch_enable_i = 1'b1; + end + + program testbench (mem_if instr_if); + logic [7:0] imem [400]; + logic [63:0] address; + // instruction memory + initial begin + // read mem file + $readmemh("add_test.v", imem, 64'b0); + $display("Read instruction memory file"); + instr_if.mck.data_rdata <= 32'b0; + // apply stimuli for instruction interface + forever begin + // instr_if.mck.data_rvalid <= 1'b0; + instr_if.mck.data_gnt <= 1'b0; + @(instr_if.mck iff instr_if.mck.data_req) + // while (instr_if.mck.data_req) begin + address <= instr_if.mck.address; + instr_if.mck.data_gnt <= 1'b1; + instr_if.mck.data_rvalid <= 1'b0; + $display("Address %0h", address); + @(instr_if.mck) + instr_if.mck.data_rvalid <= 1'b1; + instr_if.mck.data_rdata <= { + imem[$unsigned(address + 3)], + imem[$unsigned(address + 2)], + imem[$unsigned(address + 1)], + imem[$unsigned(address + 0)] + }; + // end + end + end endprogram testbench tb(instr_if); diff --git a/wave.do b/wave.do new file mode 100644 index 000000000..83bd3f5aa --- /dev/null +++ b/wave.do @@ -0,0 +1,254 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group instr_if /core_tb/instr_if/clk +add wave -noupdate -group instr_if /core_tb/instr_if/address +add wave -noupdate -group instr_if /core_tb/instr_if/data_wdata +add wave -noupdate -group instr_if /core_tb/instr_if/data_req +add wave -noupdate -group instr_if /core_tb/instr_if/data_gnt +add wave -noupdate -group instr_if /core_tb/instr_if/data_rvalid +add wave -noupdate -group instr_if /core_tb/instr_if/data_rdata +add wave -noupdate -group instr_if /core_tb/instr_if/data_we +add wave -noupdate -group instr_if /core_tb/instr_if/data_be +add wave -noupdate -group Core /core_tb/dut/clk_i +add wave -noupdate -group Core /core_tb/dut/rst_n +add wave -noupdate -group Core /core_tb/dut/clock_en_i +add wave -noupdate -group Core /core_tb/dut/test_en_i +add wave -noupdate -group Core /core_tb/dut/fetch_enable_i +add wave -noupdate -group Core /core_tb/dut/core_busy_o +add wave -noupdate -group Core /core_tb/dut/ext_perf_counters_i +add wave -noupdate -group Core /core_tb/dut/boot_addr_i +add wave -noupdate -group Core /core_tb/dut/core_id_i +add wave -noupdate -group Core /core_tb/dut/cluster_id_i +add wave -noupdate -group Core /core_tb/dut/irq_i +add wave -noupdate -group Core /core_tb/dut/irq_id_i +add wave -noupdate -group Core /core_tb/dut/irq_ack_o +add wave -noupdate -group Core /core_tb/dut/irq_sec_i +add wave -noupdate -group Core /core_tb/dut/sec_lvl_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/clk_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/rst_ni +add wave -noupdate -group if /core_tb/dut/i_if_stage/req_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/if_busy_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/id_ready_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/halt_if_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_req_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_addr_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_gnt_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rvalid_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rdata_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_valid_id_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_rdata_id_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/is_compressed_id_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/illegal_c_insn_id_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/pc_if_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/pc_id_o +add wave -noupdate -group if /core_tb/dut/i_if_stage/boot_addr_i +add wave -noupdate -group if /core_tb/dut/i_if_stage/if_ready +add wave -noupdate -group if /core_tb/dut/i_if_stage/if_valid +add wave -noupdate -group if /core_tb/dut/i_if_stage/branch_req +add wave -noupdate -group if /core_tb/dut/i_if_stage/valid +add wave -noupdate -group if /core_tb/dut/i_if_stage/prefetch_busy +add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_addr_n +add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_valid +add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_ready +add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_rdata +add wave -noupdate -group if /core_tb/dut/i_if_stage/fetch_addr +add wave -noupdate -group if /core_tb/dut/i_if_stage/offset_fsm_cs +add wave -noupdate -group if /core_tb/dut/i_if_stage/offset_fsm_ns +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_decompressed +add wave -noupdate -group if /core_tb/dut/i_if_stage/illegal_c_insn +add wave -noupdate -group if /core_tb/dut/i_if_stage/instr_compressed_int +add wave -noupdate -group if /core_tb/dut/i_if_stage/clear_instr_valid_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/clk +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/rst_n +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/req_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/branch_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/ready_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/valid_o +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_o +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/rdata_o +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_req_o +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_gnt_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_addr_o +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_rdata_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_rvalid_i +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/busy_o +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/CS +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/NS +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/instr_addr_q +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fetch_addr +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/addr_valid +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_valid +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_ready +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/fifo_clear +add wave -noupdate -group prefetcher /core_tb/dut/i_if_stage/prefetch_buffer_i/valid_stored +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/clk_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rst_ni +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/test_en_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/flush_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/instruction_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/instruction_valid_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/pc_if_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/ex_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/ready_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operator_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operand_a_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/operand_b_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/trans_id_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/alu_ready_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/alu_valid_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/lsu_ready_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/lsu_valid_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/mult_ready_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/mult_valid_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/trans_id_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wdata_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wb_valid_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/waddr_a_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/wdata_a_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/we_a_i +add wave -noupdate -expand -group id_stage -expand /core_tb/dut/id_stage_i/commit_instr_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/commit_ack_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/full_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rd_clobber_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs1_valid_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/rs2_valid_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_instr_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/decoded_instr_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_instr_valid_o +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/issue_ack_i +add wave -noupdate -expand -group id_stage /core_tb/dut/id_stage_i/illegal_instr_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/clk_i +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/rst_ni +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operator_i +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operand_a_i +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/operand_b_i +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/trans_id_i +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_ready_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_i +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_valid_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_result_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/alu_trans_id_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/comparison_result_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/lsu_ready_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/lsu_valid_i +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/mult_ready_o +add wave -noupdate -expand -group ex_stage /core_tb/dut/ex_stage_i/mult_valid_i +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/clk_i +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/rst_ni +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/pc_i +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_i +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/ex_i +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instruction_o +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/illegal_instr_o +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/instr +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_select +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_i_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_iz_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_sb_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_u_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_uj_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_z_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s2_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_bi_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_s3_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vs_type +add wave -noupdate -group decoder /core_tb/dut/id_stage_i/decoder_i/imm_vu_type +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operator_i +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_i +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_i +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_o +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result_ext_o +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/result_o +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/comparison_result_o +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal_result_o +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_a_rev32 +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/operand_b_neg +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_op_b_negate +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_a +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_in_b +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/adder_result +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_arithmetic +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_amt +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a32 +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_result32 +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_right_result32 +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_left_result32 +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_64 +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/shift_op_a_32 +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_equal +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/is_greater_equal +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_signed +add wave -noupdate -expand -group ALU /core_tb/dut/ex_stage_i/alu_i/cmp_result +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/clk_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rst_ni +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/test_en_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/flush_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_instr_valid_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/issue_ack_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs1_valid_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rs2_valid_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/rd_clobber_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_ready_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_ready_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/lsu_valid_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_ready_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/mult_valid_o +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/waddr_a_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/wdata_a_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/we_a_i +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/stall +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/fu_busy +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_regfile +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_regfile +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_n +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_a_q +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_n +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operand_b_q +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_n +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/alu_valid_q +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_n +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/trans_id_q +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_n +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/operator_q +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs1 +add wave -noupdate -expand -group issue_read_operands /core_tb/dut/id_stage_i/issue_read_operands_i/forward_rs2 +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {499 ns} 0} {{Cursor 2} {278 ns} 1} +quietly wave cursor active 1 +configure wave -namecolwidth 241 +configure wave -valuecolwidth 258 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ns} {840 ns}