From 061694e3df38a1973945355ef47bc7788aea544d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= <61976467+ASintzoff@users.noreply.github.com> Date: Tue, 14 Nov 2023 13:28:20 +0100 Subject: [PATCH] csr regfile: force `mstatus.UBE` to `0` (see #1417) (#1626) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit as CVA6 is little endian Signed-off-by: André Sintzoff --- core/csr_regfile.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index e500ac834..86b034217 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -789,6 +789,7 @@ module csr_regfile mstatus_d.wpri1 = 1'b0; mstatus_d.wpri2 = 1'b0; mstatus_d.wpri0 = 1'b0; + mstatus_d.ube = 1'b0; // CVA6 is little-endian // this register has side-effects on other registers, flush the pipeline flush_o = 1'b1; end