diff --git a/Makefile b/Makefile
index 564cc7992..3b42a5255 100755
--- a/Makefile
+++ b/Makefile
@@ -112,12 +112,12 @@ $(library):
 
 sim: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug\
+	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug +jtag_rbb_enable=1 \
 	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "run -all; do tb/wave/wave_core.do; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
 
 simc: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug\
+	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug +jtag_rbb_enable=1 \
 	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "run -all; do tb/wave/wave_core.do; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
 
 run-asm-tests: build
diff --git a/src/debug/dmi_jtag.sv b/src/debug/dmi_jtag.sv
index 2abd487d7..bfdd9180b 100644
--- a/src/debug/dmi_jtag.sv
+++ b/src/debug/dmi_jtag.sv
@@ -36,7 +36,8 @@ module dmi_jtag (
     input  logic        tms_i,    // JTAG test mode select pad
     input  logic        trst_ni,  // JTAG test reset pad
     input  logic        td_i,     // JTAG test data input pad
-    output logic        td_o      // JTAG test data output pad
+    output logic        td_o,     // JTAG test data output pad
+    output logic        tdo_oe_o  // Data out output enable
 );
 
     logic        test_logic_reset;
@@ -193,6 +194,7 @@ module dmi_jtag (
         .trst_ni,
         .td_i,
         .td_o,
+        .tdo_oe_o,
         .test_logic_reset_o ( test_logic_reset ),
         .run_test_idle_o    ( run_test_idle    ),
         .shift_dr_o         ( shift_dr         ),
diff --git a/src/debug/dmi_jtag_tap.sv b/src/debug/dmi_jtag_tap.sv
index 4c1503507..57bab9f48 100644
--- a/src/debug/dmi_jtag_tap.sv
+++ b/src/debug/dmi_jtag_tap.sv
@@ -24,7 +24,7 @@ module dmi_jtag_tap #(
     input  logic        trst_ni,  // JTAG test reset pad
     input  logic        td_i,     // JTAG test data input pad
     output logic        td_o,     // JTAG test data output pad
-
+    output logic        tdo_oe_o, // Data out output enable
     output logic        test_logic_reset_o,
     output logic        run_test_idle_o,
     output logic        shift_dr_o,
@@ -88,25 +88,25 @@ module dmi_jtag_tap #(
 
         // capture IR register
         if (capture_ir) begin
-            jtag_ir_d =  'b0101;
+            jtag_ir_shift_d =  'b0101;
         end
 
         // update IR register
-        if (capture_ir) begin
+        if (update_ir) begin
             jtag_ir_d = jtag_ir_shift_q;
         end
 
         // synchronous test-logic reset
         if (test_logic_reset_o) begin
+            jtag_ir_shift_d = '0;
             jtag_ir_d       = IDCODE;
-            jtag_ir_shift_d = IDCODE;
         end
     end
 
     always_ff @(posedge tck_i, negedge trst_ni) begin
         if (~trst_ni) begin
-            jtag_ir_shift_q <= IDCODE;
-            jtag_ir_q       <= '0;
+            jtag_ir_shift_q <= '0;
+            jtag_ir_q       <= IDCODE;
         end else begin
             jtag_ir_shift_q <= jtag_ir_shift_q;
             jtag_ir_q       <= jtag_ir_d;
@@ -207,9 +207,11 @@ module dmi_jtag_tap #(
   // TDO changes state at negative edge of TCK
     always_ff @(negedge tck_i, negedge trst_ni) begin
         if (~trst_ni) begin
-            td_o <= 1'b0;
+            td_o     <= 1'b0;
+            tdo_oe_o <= 1'b0;
         end else begin
-            td_o <= tdo_mux;
+            td_o     <= tdo_mux;
+            tdo_oe_o <= (shift_ir | shift_dr_o);
         end
     end
     // ----------------
@@ -232,7 +234,7 @@ module dmi_jtag_tap #(
 
         case (tap_state_q)
             TestLogicReset: begin
-                test_logic_reset_o = 1'b0;
+                test_logic_reset_o = 1'b1;
                 tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
             end
             RunTestIdle: begin
diff --git a/tb b/tb
index e0187d11b..df5aa1a3d 160000
--- a/tb
+++ b/tb
@@ -1 +1 @@
-Subproject commit e0187d11b81c1c27a20b4f514a4be2b2bd75ced7
+Subproject commit df5aa1a3dd68622764793c367265b01b2c96ea0c