diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv
index 347c60345..b8886e5a8 100644
--- a/src/csr_regfile.sv
+++ b/src/csr_regfile.sv
@@ -542,9 +542,21 @@ module csr_regfile #(
             end
 
             // single step enable and we just retired an instruction
-            if (dcsr_q.step && (|commit_ack_i)) begin
-                // we saved the correct target address during execute
-                dpc_d = commit_instr_i[0].bp.predict_address;
+            if (dcsr_q.step && commit_ack_i[0]) begin
+                // valid CTRL flow change
+                if (commit_instr_i[0].fu == CTRL_FLOW) begin
+                    // we saved the correct target address during execute
+                    dpc_d = commit_instr_i[0].bp.predict_address;
+                // exception valid
+                end else if (ex_i.valid) begin
+                    dpc_d = trap_vector_base_o;
+                // return from environment
+                end else if (eret_o) begin
+                    dpc_d = epc_o;
+                // consecutive PC
+                end else begin
+                    dpc_d = commit_instr_i[0].pc + (commit_instr_i[0].is_compressed ? 'h2 : 'h4);
+                end
                 debug_mode_d = 1'b1;
                 set_debug_pc_o = 1'b1;
                 dcsr_d.cause = dm::CauseSingleStep;
diff --git a/src/scoreboard.sv b/src/scoreboard.sv
index 5ed3e587e..52d8d7647 100644
--- a/src/scoreboard.sv
+++ b/src/scoreboard.sv
@@ -124,9 +124,7 @@ module scoreboard #(
                 mem_n[trans_id_i[i]].sbe.valid  = 1'b1;
                 mem_n[trans_id_i[i]].sbe.result = wbdata_i[i];
                 // save the target address of a branch (needed for debug in commit stage)
-                if (resolved_branch_i.valid) begin
-                    mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
-                end
+                mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
                 // write the exception back if it is valid
                 if (ex_i[i].valid) begin
                     mem_n[trans_id_i[i]].sbe.ex = ex_i[i];