From 17f430429f09dd5e1081af7c8015f7db1d9adca2 Mon Sep 17 00:00:00 2001
From: Jimmy Situ <web@jimmystone.cn>
Date: Tue, 8 Oct 2019 16:48:29 +0800
Subject: [PATCH] fpga: Fix empty match file in flow (#334)

---
 fpga/scripts/run.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl
index 0b011a4b6..d85cc23e6 100644
--- a/fpga/scripts/run.tcl
+++ b/fpga/scripts/run.tcl
@@ -39,7 +39,7 @@ if {$::env(BOARD) eq "genesys2"} {
     exit 1
 }
 
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*$registers"]]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*/$registers"]]
 set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
 
 update_compile_order -fileset sources_1