diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv index b8e7e0df5..467ebd552 100644 --- a/include/ariane_pkg.sv +++ b/include/ariane_pkg.sv @@ -162,8 +162,8 @@ package ariane_pkg; localparam bit RVD = riscv::IS_XLEN64; // Is D extension enabled `else // Floating-point extensions configuration - localparam bit RVF = riscv::IS_XLEN64; // Is F extension enabled - localparam bit RVD = riscv::IS_XLEN64; // Is D extension enabled + localparam bit RVF = (riscv::IS_XLEN64 | riscv::IS_XLEN32) & riscv::FPU_EN; // Is F extension enabled for both 32 Bit and 64 bit CPU + localparam bit RVD = (riscv::IS_XLEN64 ? 1:0) & riscv::FPU_EN; // Is D extension enabled for only 64 bit CPU `endif localparam bit RVA = 1'b1; // Is A extension enabled diff --git a/include/riscv_pkg.sv b/include/riscv_pkg.sv index 10ddf8073..28e7ed001 100644 --- a/include/riscv_pkg.sv +++ b/include/riscv_pkg.sv @@ -35,6 +35,7 @@ package riscv; localparam VLEN = (XLEN == 32) ? 32 : 64; // virtual address length localparam PLEN = (XLEN == 32) ? 32 : 56; // physical address length + localparam IS_XLEN32 = (XLEN == 32) ? 1'b1 : 1'b0; localparam IS_XLEN64 = (XLEN == 32) ? 1'b0 : 1'b1; localparam ModeW = (XLEN == 32) ? 1 : 4; localparam ASIDW = (XLEN == 32) ? 9 : 16; @@ -43,6 +44,8 @@ package riscv; localparam SV = (MODE_SV == ModeSv32) ? 32 : 39; localparam VPN2 = (VLEN-31 < 8) ? VLEN-31 : 8; + localparam FPU_EN = 1'b1; // This bit is to select FPU in the design, FPU_EN = 1'b0 disables FPU in the design + typedef logic [XLEN-1:0] xlen_t; // -------------------- diff --git a/src/fpu_wrap.sv b/src/fpu_wrap.sv index ecbaf7f19..958590da1 100644 --- a/src/fpu_wrap.sv +++ b/src/fpu_wrap.sv @@ -51,7 +51,7 @@ module fpu_wrap import ariane_pkg::*; ( // Features (enabled formats, vectors etc.) localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ - Width: 64, + Width: riscv::XLEN, // parameterized using XLEN EnableVectors: ariane_pkg::XFVEC, EnableNanBox: 1'b1, FpFmtMask: {RVF, RVD, XF16, XF8, XF16ALT},