From 20bd972e1d57fe52dccc1e5001b3eb446148d0d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= Date: Fri, 21 Mar 2025 14:02:37 +0100 Subject: [PATCH] multiplier.sv: improve code coverage in mult.sv, mul_valid_op (becoming mult_valid_i in multiplier.sv) is already computed with && (operation_i inside {MUL, MULH, MULHU, MULHSU, MULW, CLMUL, CLMULH, CLMULR}) Therefore, this operation is useless in multiplier.sv --- core/multiplier.sv | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/core/multiplier.sv b/core/multiplier.sv index b6c44f7f7..52e7302ee 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -83,14 +83,11 @@ module multiplier // control registers logic sign_a, sign_b; - logic mult_valid; // control signals assign mult_valid_o = mult_valid_q; assign mult_trans_id_o = trans_id_q; - assign mult_valid = mult_valid_i && (operation_i inside {MUL, MULH, MULHU, MULHSU, MULW, CLMUL, CLMULH, CLMULR}); - // Sign Select MUX always_comb begin sign_a = 1'b0; @@ -158,7 +155,7 @@ module multiplier // Input silencing trans_id_q <= trans_id_i; // Output Register - mult_valid_q <= mult_valid; + mult_valid_q <= mult_valid_i; operator_q <= operator_d; mult_result_q <= mult_result_d; end