diff --git a/src/lsu.sv b/src/lsu.sv index 7992f8ad4..d32bbce71 100644 --- a/src/lsu.sv +++ b/src/lsu.sv @@ -181,23 +181,24 @@ module lsu #( // MMU e.g.: TLBs/PTW // ------------------- mmu #( - .INSTR_TLB_ENTRIES ( 16 ), - .DATA_TLB_ENTRIES ( 16 ), - .ASID_WIDTH ( ASID_WIDTH ) + .INSTR_TLB_ENTRIES ( 16 ), + .DATA_TLB_ENTRIES ( 16 ), + .ASID_WIDTH ( ASID_WIDTH ) ) mmu_i ( - .lsu_req_i ( translation_req ), - .lsu_vaddr_i ( vaddr ), - .lsu_valid_o ( translation_valid_n ), - .lsu_paddr_o ( paddr_n ), + .lsu_req_i ( translation_req ), + .lsu_vaddr_i ( vaddr ), + .lsu_valid_o ( translation_valid_n ), + .lsu_paddr_o ( paddr_n ), // connecting PTW to D$ IF (aka mem arbiter - .data_if_address_o ( address_i [0] ), - .data_if_data_wdata_o ( data_wdata_i [0] ), - .data_if_data_req_o ( data_req_i [0] ), - .data_if_data_we_o ( data_we_i [0] ), - .data_if_data_be_o ( data_be_i [0] ), - .data_if_data_gnt_i ( data_gnt_o [0] ), - .data_if_data_rvalid_i ( data_rvalid_o [0] ), - .data_if_data_rdata_i ( data_rdata_o [0] ), + .data_if_address_o ( address_i [0] ), + .data_if_data_wdata_o ( data_wdata_i [0] ), + .data_if_data_req_o ( data_req_i [0] ), + .data_if_data_we_o ( data_we_i [0] ), + .data_if_data_be_o ( data_be_i [0] ), + .data_if_tag_status_o ( data_tag_status_i[0] ), + .data_if_data_gnt_i ( data_gnt_o [0] ), + .data_if_data_rvalid_i ( data_rvalid_o [0] ), + .data_if_data_rdata_i ( data_rdata_o [0] ), .* ); @@ -206,24 +207,25 @@ module lsu #( // --------------- store_queue store_queue_i ( // store queue write port - .valid_i ( st_valid ), - .paddr_i ( paddr_q ), - .data_i ( data ), - .be_i ( be ), + .valid_i ( st_valid ), + .paddr_i ( paddr_q ), + .data_i ( data ), + .be_i ( be ), // store buffer in - .paddr_o ( st_buffer_paddr ), - .data_o ( st_buffer_data ), - .valid_o ( st_buffer_valid ), - .be_o ( st_buffer_be ), - .ready_o ( st_ready ), + .paddr_o ( st_buffer_paddr ), + .data_o ( st_buffer_data ), + .valid_o ( st_buffer_valid ), + .be_o ( st_buffer_be ), + .ready_o ( st_ready ), - .address_o ( address_i [2] ), - .data_wdata_o ( data_wdata_i [2] ), - .data_req_o ( data_req_i [2] ), - .data_we_o ( data_we_i [2] ), - .data_be_o ( data_be_i [2] ), - .data_gnt_i ( data_gnt_o [2] ), - .data_rvalid_i ( data_rvalid_o[2] ), + .address_o ( address_i [2] ), + .data_wdata_o ( data_wdata_i [2] ), + .data_req_o ( data_req_i [2] ), + .data_we_o ( data_we_i [2] ), + .data_be_o ( data_be_i [2] ), + .data_tag_status_o ( data_tag_status_i[2] ), + .data_gnt_i ( data_gnt_o [2] ), + .data_rvalid_i ( data_rvalid_o [2] ), .* ); @@ -371,7 +373,7 @@ module lsu #( translation_req = 1'b1; // check if this operation is a load or store // it is a LOAD - if (operator == LD_OP) begin + if (op == LD_OP) begin data_req_i[1] = 1'b1; // request this address // if address translation is enabled wait for the tag in second (or n-th) cycle @@ -387,9 +389,10 @@ module lsu #( end end // a store does not need to pass the address conflict check because it can't conflict - end else if (operator == ST_OP) begin + end else if (op == ST_OP) begin // A store can pass through if the store buffer is not full if (st_ready) begin + translation_req = 1'b1; // e.g.: if the address was valid NS = WAIT_STORE; end else begin diff --git a/src/mmu.sv b/src/mmu.sv index 3d9812417..42bfa3f1a 100644 --- a/src/mmu.sv +++ b/src/mmu.sv @@ -67,6 +67,7 @@ module mmu #( output logic data_if_data_req_o, output logic data_if_data_we_o, output logic [7:0] data_if_data_be_o, + output logic [1:0] data_if_tag_status_o, input logic data_if_data_gnt_i, input logic data_if_data_rvalid_i, input logic [63:0] data_if_data_rdata_i @@ -172,6 +173,7 @@ module mmu #( .data_req_o ( data_if_data_req_o ), .data_we_o ( data_if_data_we_o ), .data_be_o ( data_if_data_be_o ), + .data_tag_status_o ( data_if_tag_status_o ), .data_gnt_i ( data_if_data_gnt_i ), .data_rvalid_i ( data_if_data_rvalid_i ), .data_rdata_i ( data_if_data_rdata_i ), diff --git a/src/ptw.sv b/src/ptw.sv index a98e3b335..d6574fd7d 100644 --- a/src/ptw.sv +++ b/src/ptw.sv @@ -39,6 +39,7 @@ module ptw #( output logic data_req_o, output logic data_we_o, output logic [7:0] data_be_o, + output logic [1:0] data_tag_status_o, input logic data_gnt_i, input logic data_rvalid_i, input logic [63:0] data_rdata_i, @@ -69,6 +70,7 @@ module ptw #( pte_t ptw_pte_i; assign ptw_pte_i = pte_t'(data_rdata_i); + assign data_tag_status_o = 2'b01; enum logic[1:0] { PTW_READY, diff --git a/src/store_queue.sv b/src/store_queue.sv index 347f69258..14765d35e 100644 --- a/src/store_queue.sv +++ b/src/store_queue.sv @@ -45,9 +45,11 @@ module store_queue ( output logic data_req_o, output logic data_we_o, output logic [7:0] data_be_o, + output logic [1:0] data_tag_status_o, input logic data_gnt_i, input logic data_rvalid_i ); + // the store queue has two parts: // 1. Speculative queue // 2. Commit queue which is non-speculative, e.g.: the store will definitely happen. @@ -66,16 +68,16 @@ module store_queue ( } commit_queue_n, commit_queue_q; // we can directly output the commit entry since we just have one element in this "queue" - assign paddr_o = commit_queue_q.address; - assign data_o = commit_queue_q.data; - assign be_o = commit_queue_q.be; - assign valid_o = commit_queue_q.valid; + assign paddr_o = commit_queue_q.address; + assign data_o = commit_queue_q.data; + assign be_o = commit_queue_q.be; + assign valid_o = commit_queue_q.valid; // those signals can directly be output to the memory if - assign address_o = commit_queue_q.address; - assign data_wdata_o = commit_queue_q.data; - assign data_be_o = commit_queue_q.be; - + assign address_o = commit_queue_q.address; + assign data_wdata_o = commit_queue_q.data; + assign data_be_o = commit_queue_q.be; + assign data_tag_status_o = 2'b01; // the tag is always ready since we are using physical addresses // memory interface always_comb begin : store_if // if there is no commit pending and the uncommitted queue is empty as well we can accept the request diff --git a/tb/agents/lsu_if/lsu_if.sv b/tb/agents/lsu_if/lsu_if.sv index 48df8a352..35954fa33 100644 --- a/tb/agents/lsu_if/lsu_if.sv +++ b/tb/agents/lsu_if/lsu_if.sv @@ -18,20 +18,20 @@ interface lsu_if #( input clk ); - fu_op operator; // FU operation - wire [OPERAND_SIZE-1:0] operand_a; // Operand A - wire [OPERAND_SIZE-1:0] operand_b; // Operand B - wire [OPERAND_SIZE-1:0] imm; // Operand B - wire [OPERAND_SIZE-1:0] result; // Result - wire [TRANS_ID_BITS-1:0] lsu_trans_id_id; // transaction id from ID - wire [TRANS_ID_BITS-1:0] lsu_trans_id_wb; // transaction id to WB + fu_op operator; // FU operation + wire [OPERAND_SIZE-1:0] operand_a; // Operand A + wire [OPERAND_SIZE-1:0] operand_b; // Operand B + wire [OPERAND_SIZE-1:0] imm; // Operand B + wire [OPERAND_SIZE-1:0] result; // Result + wire [TRANS_ID_BITS-1:0] lsu_trans_id_id; // transaction id from ID + wire [TRANS_ID_BITS-1:0] lsu_trans_id_wb; // transaction id to WB // LSU control signals - wire commit; - wire source_valid; // Source operands are valid - wire result_valid; // Result is valid, ready to accept new request - wire ready; // Sink is ready + wire commit; + wire source_valid; // Source operands are valid + wire result_valid; // Result is valid, ready to accept new request + wire ready; // Sink is ready // exceptions - exception exception; + wire [$bits(exception)-1:0] exception; // FU interface configured as master clocking mck @(posedge clk); diff --git a/tb/lsu_tb.sv b/tb/lsu_tb.sv index cd4d6de64..0e3e27704 100644 --- a/tb/lsu_tb.sv +++ b/tb/lsu_tb.sv @@ -61,18 +61,18 @@ module lsu_tb; .asid_i ( 1'b0 ), .flush_tlb_i ( 1'b0 ), - .instr_if_address_o ( instr_if.address ), - .instr_if_data_req_o ( instr_if.data_req ), - .instr_if_data_be_o ( instr_if.data_be ), - .instr_if_data_gnt_i ( instr_if.data_gnt ), - .instr_if_data_rvalid_i ( instr_if.data_rvalid ), - .instr_if_data_rdata_i ( instr_if.data_rdata ), + .instr_if_address_o ( instr_if.address ), + .instr_if_data_req_o ( instr_if.data_req ), + .instr_if_data_be_o ( instr_if.data_be[3:0] ), + .instr_if_data_gnt_i ( instr_if.data_gnt ), + .instr_if_data_rvalid_i ( instr_if.data_rvalid ), + .instr_if_data_rdata_i ( instr_if.data_rdata[31:0] ), - .data_if_address_o ( slave.address ), - .data_if_data_wdata_o ( slave.data_wdata ), - .data_if_data_req_o ( slave.data_req ), - .data_if_data_we_o ( slave.data_we ), - .data_if_data_be_o ( slave.data_be ), + .data_if_address_o ( slave.address ), + .data_if_data_wdata_o ( slave.data_wdata ), + .data_if_data_req_o ( slave.data_req ), + .data_if_data_we_o ( slave.data_we ), + .data_if_data_be_o ( slave.data_be ), // hack to not get a grant without a request .data_if_data_gnt_i ( slave.data_req & slave.data_gnt ), .data_if_data_rvalid_i ( slave.data_rvalid ), diff --git a/tb/wave/wave_lsu.do b/tb/wave/wave_lsu.do index 816d32253..6af2793cf 100644 --- a/tb/wave/wave_lsu.do +++ b/tb/wave/wave_lsu.do @@ -1,208 +1,9 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -expand -group LSU /lsu_tb/dut/clk_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/rst_ni -add wave -noupdate -expand -group LSU /lsu_tb/dut/flush_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/operator_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/operand_a_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/operand_b_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/imm_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/lsu_ready_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/lsu_valid_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/lsu_trans_id_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/lsu_trans_id_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/lsu_result_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/lsu_valid_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/commit_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/enable_translation_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/fetch_req_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/fetch_gnt_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/fetch_valid_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/fetch_err_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/fetch_vaddr_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/fetch_rdata_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/priv_lvl_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/flag_pum_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/flag_mxr_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/pd_ppn_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/asid_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/flush_tlb_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/lsu_exception_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/data_misaligned -add wave -noupdate -expand -group LSU /lsu_tb/dut/CS -add wave -noupdate -expand -group LSU /lsu_tb/dut/NS -add wave -noupdate -expand -group LSU /lsu_tb/dut/vaddr_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/stall -add wave -noupdate -expand -group LSU /lsu_tb/dut/get_from_register -add wave -noupdate -expand -group LSU /lsu_tb/dut/vaddr -add wave -noupdate -expand -group LSU /lsu_tb/dut/data -add wave -noupdate -expand -group LSU /lsu_tb/dut/be -add wave -noupdate -expand -group LSU /lsu_tb/dut/operator -add wave -noupdate -expand -group LSU /lsu_tb/dut/trans_id -add wave -noupdate -expand -group LSU /lsu_tb/dut/vaddr_q -add wave -noupdate -expand -group LSU /lsu_tb/dut/data_q -add wave -noupdate -expand -group LSU /lsu_tb/dut/operator_q -add wave -noupdate -expand -group LSU /lsu_tb/dut/trans_id_q -add wave -noupdate -expand -group LSU /lsu_tb/dut/st_buffer_paddr -add wave -noupdate -expand -group LSU /lsu_tb/dut/st_buffer_data -add wave -noupdate -expand -group LSU /lsu_tb/dut/st_buffer_be -add wave -noupdate -expand -group LSU /lsu_tb/dut/st_buffer_valid -add wave -noupdate -expand -group LSU /lsu_tb/dut/st_ready -add wave -noupdate -expand -group LSU /lsu_tb/dut/st_valid -add wave -noupdate -expand -group LSU /lsu_tb/dut/translation_req -add wave -noupdate -expand -group LSU /lsu_tb/dut/translation_valid -add wave -noupdate -expand -group LSU /lsu_tb/dut/paddr_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/address_i -add wave -noupdate -expand -group LSU -expand /lsu_tb/dut/data_wdata_i -add wave -noupdate -expand -group LSU -expand /lsu_tb/dut/data_req_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/data_we_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/data_be_i -add wave -noupdate -expand -group LSU /lsu_tb/dut/data_gnt_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/data_rvalid_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/data_rdata_o -add wave -noupdate -expand -group LSU /lsu_tb/dut/rdata -add wave -noupdate -expand -group LSU /lsu_tb/dut/address_match -add wave -noupdate -expand -group LSU /lsu_tb/dut/op -add wave -noupdate -expand -group LSU /lsu_tb/dut/rdata_d_ext -add wave -noupdate -expand -group LSU /lsu_tb/dut/rdata_w_ext -add wave -noupdate -expand -group LSU /lsu_tb/dut/rdata_h_ext -add wave -noupdate -expand -group LSU /lsu_tb/dut/rdata_b_ext -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/clk_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/rst_ni -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/flush_ready_o -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/address_o -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/data_wdata_o -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/data_req_o -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/data_we_o -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/data_be_o -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/data_gnt_i -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/data_rvalid_i -add wave -noupdate -expand -group mem_arbiter -expand -group Master /lsu_tb/dut/mem_arbiter_i/data_rdata_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/address_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_wdata_i -add wave -noupdate -expand -group mem_arbiter -expand /lsu_tb/dut/mem_arbiter_i/data_req_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_we_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_be_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_gnt_o -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_rvalid_o -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_rdata_o -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/full_o -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/empty_o -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/push_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/data_o -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/pop_i -add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/single_element_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/clk_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/rst_ni -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/flush_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/paddr_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/valid_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/be_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/commit_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/ready_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/valid_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/paddr_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/be_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/address_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_wdata_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_req_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_we_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_be_o -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_gnt_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/data_rvalid_i -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/commit_queue_n -add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/commit_queue_q -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/clk_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/rst_ni -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/enable_translation_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_req_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_gnt_o -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_valid_o -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_err_o -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_vaddr_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_rdata_o -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/lsu_req_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/lsu_vaddr_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/lsu_valid_o -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/lsu_paddr_o -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/priv_lvl_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/flag_pum_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/flag_mxr_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/pd_ppn_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/asid_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/flush_tlb_i -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_paddr -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/fetch_req -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/ierr_valid_q -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/ierr_valid_n -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/iaccess_err -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/ptw_active -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/walking_instr -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/ptw_error -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/update_is_2M -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/update_is_1G -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/update_vpn -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/update_asid -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/update_content -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/itlb_update -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/itlb_lu_access -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/itlb_content -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/itlb_is_2M -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/itlb_is_1G -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/itlb_lu_hit -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/dtlb_update -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/dtlb_lu_access -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/dtlb_content -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/dtlb_is_2M -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/dtlb_is_1G -add wave -noupdate -group mmu /lsu_tb/dut/i_mmu/dtlb_lu_hit -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/clk_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/rst_ni -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/flush_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_active_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/walking_instr_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_error_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/enable_translation_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/address_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/data_wdata_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/data_req_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/data_we_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/data_be_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/data_gnt_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/data_rvalid_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/data_rdata_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/itlb_update_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/dtlb_update_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/update_content_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/update_is_2M_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/update_is_1G_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/update_vpn_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/update_asid_o -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/asid_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/itlb_access_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/itlb_miss_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/itlb_vaddr_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/dtlb_access_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/dtlb_miss_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/dtlb_vaddr_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/pd_ppn_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/flag_mxr_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_pte_i -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_state_q -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_state_n -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_lvl_q -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_lvl_n -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/is_instr_ptw_q -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/is_instr_ptw_n -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/tlb_update_asid_q -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/tlb_update_asid_n -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/tlb_update_vpn_q -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/tlb_update_vpn_n -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_pptr_q -add wave -noupdate -group PTW /lsu_tb/dut/i_mmu/ptw_i/ptw_pptr_n +add wave -noupdate -expand -group LSU /lsu_tb/dut/* +add wave -noupdate -expand -group mem_arbiter /lsu_tb/dut/mem_arbiter_i/* +add wave -noupdate -group store_queue /lsu_tb/dut/store_queue_i/* +add wave -noupdate -group mmu /lsu_tb/dut/mmu_i/* TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {454 ns} 0} quietly wave cursor active 1