diff --git a/verif/env/uvme/cov/uvme_exception_covg.sv b/verif/env/uvme/cov/uvme_exception_covg.sv index 123d865cd..d56e868ae 100644 --- a/verif/env/uvme/cov/uvme_exception_covg.sv +++ b/verif/env/uvme/cov/uvme_exception_covg.sv @@ -35,14 +35,13 @@ covergroup cg_exception( `ifndef QUESTA cp_exception: coverpoint instr.cause { - bins NO_EXCEPTION = {0} iff (!instr.trap); bins BREAKPOINT = {3} iff (instr.trap); bins ILLEGAL_INSTR = {2} iff (instr.trap); ignore_bins IGN_ADDR_MISALIGNED_EXC = {0, 4, 6} iff (unaligned_access_supported); - ignore_bins IGN_INSTR_ADDR_MISALIGNED_EXC = {0} iff (ext_c_supported && instr.trap); + ignore_bins IGN_INSTR_ADDR_MISALIGNED_EXC = {0} iff (ext_c_supported); bins INSTR_ADDR_MISALIGNED = {0} iff (instr.trap); bins LD_ADDR_MISALIGNED = {4} iff (instr.trap); @@ -75,6 +74,11 @@ covergroup cg_exception( } + cp_trap: coverpoint instr.trap { + bins is_trap = {1}; + bins no_trap = {0}; + } + cp_is_ebreak: coverpoint instr.name { bins is_ebreak = {uvma_isacov_pkg::EBREAK, uvma_isacov_pkg::C_EBREAK}; @@ -96,14 +100,16 @@ covergroup cg_exception( bins is_csr_write = {1}; } + cp_is_not_write_csr: coverpoint instr.is_csr_write() { + bins is_not_csr_write = {0}; + } + cp_illegal_csr: coverpoint instr.csr { - bins UNSUPPORTED_CSR[] = {[uvma_isacov_pkg::USTATUS:uvma_isacov_pkg::VLENB]} with (cfg_illegal_csr[item] == 1) iff(instr.trap); + bins UNSUPPORTED_CSR[] = {[uvma_isacov_pkg::USTATUS:uvma_isacov_pkg::MCONFIGPTR]} with (cfg_illegal_csr[item] == 1); } cp_ro_csr: coverpoint instr.csr { - bins ONLY_READ_CSR[] = {[uvma_isacov_pkg::CYCLE:uvma_isacov_pkg::HPMCOUNTER31], - [uvma_isacov_pkg::CYCLEH:uvma_isacov_pkg::HPMCOUNTER31H], - [uvma_isacov_pkg::MVENDORID:uvma_isacov_pkg::MHARTID]} with (cfg_illegal_csr[item] == 0) iff(instr.trap); + bins ONLY_READ_CSR[] = {[uvma_isacov_pkg::USTATUS:uvma_isacov_pkg::MCONFIGPTR]} with ((cfg_illegal_csr[item] == 0) && (item[11:10] == 2'b11)); } cp_misalign_load: coverpoint instr.group { @@ -130,7 +136,7 @@ covergroup cg_exception( ignore_bins IGN = !binsof(cp_exception) intersect{2}; } - cross_illegal_csr : cross cp_exception, cp_illegal_csr, cp_is_csr { + cross_illegal_csr : cross cp_exception, cp_illegal_csr, cp_is_csr, cp_is_not_write_csr { ignore_bins IGN = !binsof(cp_exception) intersect{2}; } diff --git a/verif/env/uvme/reg/cva6_csr_reg_block.sv b/verif/env/uvme/reg/cva6_csr_reg_block.sv index fe4be6f3c..990ed7a8d 100644 --- a/verif/env/uvme/reg/cva6_csr_reg_block.sv +++ b/verif/env/uvme/reg/cva6_csr_reg_block.sv @@ -144,10 +144,6 @@ class cva6_csr_reg_block extends uvm_reg_block; rand reg_mhpmcounterh29 mhpmcounterh29; rand reg_mhpmcounterh30 mhpmcounterh30; rand reg_mhpmcounterh31 mhpmcounterh31; - rand reg_cycle cycle; - rand reg_instret instret; - rand reg_cycleh cycleh; - rand reg_instreth instreth; rand reg_mvendorid mvendorid; rand reg_marchid marchid; rand reg_mimpid mimpid; @@ -656,22 +652,6 @@ class cva6_csr_reg_block extends uvm_reg_block; mhpmcounterh31.configure(this, null, "mhpmcounterh31"); mhpmcounterh31.build(); - cycle = reg_cycle::type_id::create("cycle", null, get_full_name()); - cycle.configure(this, null, "cycle"); - cycle.build(); - - instret = reg_instret::type_id::create("instret", null, get_full_name()); - instret.configure(this, null, "instret"); - instret.build(); - - cycleh = reg_cycleh::type_id::create("cycleh", null, get_full_name()); - cycleh.configure(this, null, "cycleh"); - cycleh.build(); - - instreth = reg_instreth::type_id::create("instreth", null, get_full_name()); - instreth.configure(this, null, "instreth"); - instreth.build(); - mvendorid = reg_mvendorid::type_id::create("mvendorid", null, get_full_name()); mvendorid.configure(this, null, "mvendorid"); mvendorid.build(); @@ -815,11 +795,7 @@ class cva6_csr_reg_block extends uvm_reg_block; default_map.add_reg(mhpmcounterh28, 'hb9c, "RW"); default_map.add_reg(mhpmcounterh29, 'hb9d, "RW"); default_map.add_reg(mhpmcounterh30, 'hb9e, "RW"); - default_map.add_reg(mhpmcounterh31, 'hb9f, "RW"); - default_map.add_reg(cycle, 'hC00, "RO"); - default_map.add_reg(instret, 'hC02, "RO"); - default_map.add_reg(cycleh, 'hC80, "RO"); - default_map.add_reg(instreth, 'hC82, "RO"); + default_map.add_reg(mhpmcounterh31, 'hb9f, "RW"); default_map.add_reg(mvendorid, 'hF11, "RO"); default_map.add_reg(marchid, 'hF12, "RO"); default_map.add_reg(mimpid, 'hF13, "RO"); diff --git a/verif/env/uvme/reg/cva6_csr_reg_file.sv b/verif/env/uvme/reg/cva6_csr_reg_file.sv index faec2146e..5f3ca08bc 100644 --- a/verif/env/uvme/reg/cva6_csr_reg_file.sv +++ b/verif/env/uvme/reg/cva6_csr_reg_file.sv @@ -86,36 +86,67 @@ class reg_mstatus extends csr_reg; option.per_instance = 1; SD: coverpoint data[31:31] { bins legal_values[] = {0}; - //GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + TSR: coverpoint data[22:22] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + TW: coverpoint data[21:21] { + bins legal_values[] = {0}; + // issue#2228 illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + // TODO : need configuration on these coverpoints + TVM: coverpoint data[20:20] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + MXR: coverpoint data[19:19] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + SUM: coverpoint data[18:18] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + MPRV: coverpoint data[17:17] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); } - TSR: coverpoint data[22:22]; - TW: coverpoint data[21:21]; - TVM: coverpoint data[20:20]; - MXR: coverpoint data[19:19]; - SUM: coverpoint data[18:18]; - MPRV: coverpoint data[17:17]; XS: coverpoint data[16:15] { bins legal_values[] = {0}; - illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); } FS: coverpoint data[14:13] { bins legal_values[] = {0}; - illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + MPP: coverpoint data[12:11] { + bins legal_values[] = {3}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {3})); } - MPP: coverpoint data[12:11]; VS: coverpoint data[10:9] { bins legal_values[] = {0}; - illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + SPP: coverpoint data[8:8] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); } - SPP: coverpoint data[8:8]; MPIE: coverpoint data[7:7]; UBE: coverpoint data[6:6] { bins legal_values[] = {0}; - illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } + SPIE: coverpoint data[5:5] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); } - SPIE: coverpoint data[5:5]; MIE: coverpoint data[3:3]; - SIE: coverpoint data[1:1]; + SIE: coverpoint data[1:1] { + bins legal_values[] = {0}; + ignore_bins illegal_values = {[0:$]} with (!(item inside {0})); + } endgroup covergroup reg_wr_cg with function sample(uvm_reg_data_t data); @@ -471,8 +502,8 @@ class reg_mtvec extends csr_reg; bins other_values[3] = {[1:$]}; } MODE: coverpoint data[1:0] { - bins legal_values[] = {0,1}; - illegal_bins illegal_values = {[0:$]} with (!(item inside {0,1})); + bins legal_values[] = {0}; + illegal_bins illegal_values = {[0:$]} with (!(item inside {0})); } endgroup @@ -2613,11 +2644,11 @@ class reg_mtval extends csr_reg; endgroup covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_mtval.mtval__write_cp"; + option.name = "csr_mtval__write_cg"; option.per_instance = 1; - mtval: coverpoint data[31:0]{ - bins ZERO[] = {0}; - bins other_values[3] = {[1:$]}; + mtval: coverpoint data[31:0] { + bins reset_value = {0}; + bins other_values[3] = {[1:$]}; } endgroup @@ -8092,266 +8123,6 @@ class reg_mhpmcounterh31 extends csr_reg; endclass -class reg_cycle extends csr_reg; - `uvm_object_utils(reg_cycle) - - //--------------------------------------- - // fields instance - //--------------------------------------- - rand uvm_reg_field count; - - - covergroup reg_rd_cg with function sample(uvm_reg_data_t data); - option.name = "csr_cycle__read_cg"; - option.per_instance = 1; - count: coverpoint data[31:0] { - bins reset_value = {[0:10000]}; - bins other_values[3] = {[10001:$]}; - } - count_overflow: coverpoint data[31:0] { - bins overflow = ([32'hFFFFFBFF:$] => [0:10000]); - } - endgroup - - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_cycle.cycle__write_cp"; - option.per_instance = 1; - count: coverpoint data[31:0]{ - bins reset_value = {0}; - bins other_values[3] = {[1:$]}; - } - endgroup - - //--------------------------------------- - // Constructor - //--------------------------------------- - function new (string name = "reg_cycle"); - super.new(name); - set_privilege_level(U_LEVEL); - reg_rd_cg = new(); - reg_rd_cg.set_inst_name("csr_reg_cov.cycle.cycle__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.cycle.cycle__write_cg"); - endfunction - - //--------------------------------------- - // build_phase - - // 1. Create the fields - // 2. Configure the fields - //--------------------------------------- - function void build; - - count = uvm_reg_field::type_id::create("count"); - count.configure(.parent(this), .size(32), .lsb_pos(0), .access("RO"), .volatile(0), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); - endfunction - - virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en,bit is_read, uvm_reg_map map); - if (get_coverage(UVM_CVR_FIELD_VALS)) begin - if (is_read) - reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); - end - endfunction - -endclass - - -class reg_instret extends csr_reg; - `uvm_object_utils(reg_instret) - - //--------------------------------------- - // fields instance - //--------------------------------------- - rand uvm_reg_field count; - - - covergroup reg_rd_cg with function sample(uvm_reg_data_t data); - option.name = "csr_instret__read_cg"; - option.per_instance = 1; - count: coverpoint data[31:0] { - bins reset_value = {[0:1000]}; - bins other_values[3] = {[1001:$]}; - } - count_overflow: coverpoint data[31:0] { - bins overflow = ([32'hFFFFFC17:$] => [0:100]); - } - endgroup - - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_instret.instret__write_cp"; - option.per_instance = 1; - count: coverpoint data[31:0] { - bins reset_value = {0}; - bins other_values[3] = {[1:$]}; - } - endgroup - - //--------------------------------------- - // Constructor - //--------------------------------------- - function new (string name = "reg_instret"); - super.new(name); - set_privilege_level(U_LEVEL); - reg_rd_cg = new(); - reg_rd_cg.set_inst_name("csr_reg_cov.instret.instret__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.instret.instret__write_cg"); - endfunction - - //--------------------------------------- - // build_phase - - // 1. Create the fields - // 2. Configure the fields - //--------------------------------------- - function void build; - - count = uvm_reg_field::type_id::create("count"); - count.configure(.parent(this), .size(32), .lsb_pos(0), .access("RO"), .volatile(0), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); - endfunction - - virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en,bit is_read, uvm_reg_map map); - if (get_coverage(UVM_CVR_FIELD_VALS)) begin - if (is_read) - reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); - end - endfunction - -endclass - - -class reg_cycleh extends csr_reg; - `uvm_object_utils(reg_cycleh) - - //--------------------------------------- - // fields instance - //--------------------------------------- - rand uvm_reg_field count; - - - covergroup reg_rd_cg with function sample(uvm_reg_data_t data); - option.name = "csr_cycleh__read_cg"; - option.per_instance = 1; - count: coverpoint data[31:0] { - bins reset_value = {0}; - bins other_values[3] = {[1:$]}; - } - count_overflow: coverpoint data[31:0] { - bins overflow = ([32'hFFFFFBFF:$] => [0:1000]); - } - endgroup - - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_cycleh.cycleh__write_cp"; - option.per_instance = 1; - count: coverpoint data[31:0] { - bins reset_value = {0}; - bins other_values[3] = {[1:$]}; - } - endgroup - - //--------------------------------------- - // Constructor - //--------------------------------------- - function new (string name = "reg_cycleh"); - super.new(name); - set_privilege_level(U_LEVEL); - reg_rd_cg = new(); - reg_rd_cg.set_inst_name("csr_reg_cov.cycleh.cycleh__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.cycleh.cycleh__write_cg"); - endfunction - - //--------------------------------------- - // build_phase - - // 1. Create the fields - // 2. Configure the fields - //--------------------------------------- - function void build; - - count = uvm_reg_field::type_id::create("count"); - count.configure(.parent(this), .size(32), .lsb_pos(0), .access("RO"), .volatile(0), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); - endfunction - - virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en,bit is_read, uvm_reg_map map); - if (get_coverage(UVM_CVR_FIELD_VALS)) begin - if (is_read) - reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); - end - endfunction - -endclass - - -class reg_instreth extends csr_reg; - `uvm_object_utils(reg_instreth) - - //--------------------------------------- - // fields instance - //--------------------------------------- - rand uvm_reg_field count; - - - covergroup reg_rd_cg with function sample(uvm_reg_data_t data); - option.name = "csr_instreth__read_cg"; - option.per_instance = 1; - count: coverpoint data[31:0] { - bins reset_value = {0}; - bins other_values[3] = {[1:$]}; - } - count_overflow: coverpoint data[31:0] { - bins overflow = ([32'hFFFFFFEF:$] => [0:10]); - } - endgroup - - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_instreth.instreth__write_cp"; - option.per_instance = 1; - count: coverpoint data[31:0] { - bins reset_value = {0}; - bins other_values[3] = {[1:$]}; - } - endgroup - - //--------------------------------------- - // Constructor - //--------------------------------------- - function new (string name = "reg_instreth"); - super.new(name); - set_privilege_level(U_LEVEL); - reg_rd_cg = new(); - reg_rd_cg.set_inst_name("csr_reg_cov.instreth.instreth__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.instreth.instreth__write_cg"); - endfunction - - //--------------------------------------- - // build_phase - - // 1. Create the fields - // 2. Configure the fields - //--------------------------------------- - function void build; - - count = uvm_reg_field::type_id::create("count"); - count.configure(.parent(this), .size(32), .lsb_pos(0), .access("RO"), .volatile(0), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); - endfunction - - virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en,bit is_read, uvm_reg_map map); - if (get_coverage(UVM_CVR_FIELD_VALS)) begin - if (is_read) - reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); - end - endfunction - -endclass - - class reg_mvendorid extends csr_reg; `uvm_object_utils(reg_mvendorid) @@ -8373,19 +8144,6 @@ class reg_mvendorid extends csr_reg; } endgroup - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_mvendorid.mvendorid__write_cp"; - option.per_instance = 1; - bank: coverpoint data[31:7] { - bins reset_value = {'hC}; - bins other_values[3] = {[0:$]} with (!(item inside {'hC0})); - } - offset: coverpoint data[6:0]{ - bins reset_value = {'h2}; - bins other_values[3] = {[0:$]} with (!(item inside {'h20})); - } - endgroup - //--------------------------------------- // Constructor //--------------------------------------- @@ -8394,8 +8152,6 @@ class reg_mvendorid extends csr_reg; set_privilege_level(M_LEVEL); reg_rd_cg = new(); reg_rd_cg.set_inst_name("csr_reg_cov.mvendorid.mvendorid__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.mvendorid.mvendorid__write_cg"); endfunction //--------------------------------------- @@ -8416,8 +8172,6 @@ class reg_mvendorid extends csr_reg; if (get_coverage(UVM_CVR_FIELD_VALS)) begin if (is_read) reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); end endfunction @@ -8441,15 +8195,6 @@ class reg_marchid extends csr_reg; } endgroup - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_marchid.marchid__write_cp"; - option.per_instance = 1; - architecture_id: coverpoint data[31:0] { - bins reset_value = {'h3}; - bins other_values[3] = {[0:$]} with (!(item inside {'h3})); - } - endgroup - //--------------------------------------- // Constructor //--------------------------------------- @@ -8458,8 +8203,6 @@ class reg_marchid extends csr_reg; set_privilege_level(M_LEVEL); reg_rd_cg = new(); reg_rd_cg.set_inst_name("csr_reg_cov.marchid.marchid__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.marchid.marchid__write_cg"); endfunction //--------------------------------------- @@ -8477,8 +8220,6 @@ class reg_marchid extends csr_reg; if (get_coverage(UVM_CVR_FIELD_VALS)) begin if (is_read) reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); end endfunction @@ -8502,15 +8243,6 @@ class reg_mimpid extends csr_reg; } endgroup - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_mimpid.mimpid__write_cp"; - option.per_instance = 1; - implementation: coverpoint data[31:0] { - bins reset_value = {0}; - bins other_values[3] = {[0:$]} with (!(item inside {0})); - } - endgroup - //--------------------------------------- // Constructor //--------------------------------------- @@ -8519,8 +8251,6 @@ class reg_mimpid extends csr_reg; set_privilege_level(M_LEVEL); reg_rd_cg = new(); reg_rd_cg.set_inst_name("csr_reg_cov.mimpid.mimpid__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.mimpid.mimpid__write_cg"); endfunction //--------------------------------------- @@ -8538,8 +8268,6 @@ class reg_mimpid extends csr_reg; if (get_coverage(UVM_CVR_FIELD_VALS)) begin if (is_read) reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); end endfunction @@ -8563,15 +8291,6 @@ class reg_mhartid extends csr_reg; } endgroup - covergroup reg_wr_cg with function sample(uvm_reg_data_t data); - option.name = "csr_mhartid.mhartid__write_cp"; - option.per_instance = 1; - hart_id: coverpoint data[31:0] { - bins reset_value = {0}; - bins other_values[3] = {[0:$]} with (!(item inside {0})); - } - endgroup - //--------------------------------------- // Constructor //--------------------------------------- @@ -8580,8 +8299,6 @@ class reg_mhartid extends csr_reg; set_privilege_level(M_LEVEL); reg_rd_cg = new(); reg_rd_cg.set_inst_name("csr_reg_cov.mhartid.mhartid__read_cg"); - reg_wr_cg = new(); - reg_wr_cg.set_inst_name("csr_reg_cov.mhartid.mhartid__write_cg"); endfunction //--------------------------------------- @@ -8599,8 +8316,6 @@ class reg_mhartid extends csr_reg; if (get_coverage(UVM_CVR_FIELD_VALS)) begin if (is_read) reg_rd_cg.sample(data); - else - reg_wr_cg.sample(data); end endfunction diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv index 06d791a6d..e81152dcf 100644 --- a/verif/env/uvme/uvme_cva6_cfg.sv +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -48,11 +48,19 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; // Zicond extension rand bit ext_zicond_supported; + + // HPDcache support rand bit HPDCache_supported; - //pmp entries + // pmp entries rand int nr_pmp_entries; + // Zihpm extension + rand bit ext_zihpm_supported; + + // hypervisor mode + rand bit mode_h_supported; + // Handle to RTL configuration rand cva6_cfg_t CVA6Cfg; @@ -66,6 +74,8 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; `uvm_field_int ( ext_zicond_supported , UVM_DEFAULT ) `uvm_field_int ( HPDCache_supported , UVM_DEFAULT ) `uvm_field_int ( nr_pmp_entries , UVM_DEFAULT ) + `uvm_field_int ( ext_zihpm_supported , UVM_DEFAULT ) + `uvm_field_int ( mode_h_supported , UVM_DEFAULT ) `uvm_field_int ( sys_clk_period , UVM_DEFAULT + UVM_DEC) `uvm_field_object(clknrst_cfg, UVM_DEFAULT) @@ -125,9 +135,12 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; ext_zicsr_supported == 1; ext_zicond_supported == CVA6Cfg.RVZiCond; ext_zcb_supported == CVA6Cfg.RVZCB; + ext_zihpm_supported == 0; + ext_zicntr_supported == 0; mode_s_supported == CVA6Cfg.RVS; mode_u_supported == CVA6Cfg.RVU; + mode_h_supported == CVA6Cfg.RVH; pmp_supported == (CVA6Cfg.NrPMPEntries > 0); nr_pmp_entries == 16; @@ -284,7 +297,6 @@ function void uvme_cva6_cfg_c::set_unsupported_csr_mask(); super.set_unsupported_csr_mask(); // Remove unsupported CSRs for Embedded configuration - unsupported_csr_mask[uvma_core_cntrl_pkg::MTVAL] = 1; unsupported_csr_mask[uvma_core_cntrl_pkg::MTVAL2] = 1; unsupported_csr_mask[uvma_core_cntrl_pkg::MCOUNTINHIBIT] = 1; unsupported_csr_mask[uvma_core_cntrl_pkg::MTINST] = 1; @@ -292,15 +304,46 @@ function void uvme_cva6_cfg_c::set_unsupported_csr_mask(); // Add supported CSRs for Embedded configuration for (int i = 0; i < MAX_NUM_HPMCOUNTERS; i++) begin unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMEVENT3+i] = 0; - unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3+i] = 0; - unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3H+i] = 0; + if (xlen == 32) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3+i] = 0; + unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3H+i] = 0; + end + else if (xlen == 64) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3+i] = 1; + unsupported_csr_mask[uvma_core_cntrl_pkg::MHPMCOUNTER3H+i] = 1; + end end - unsupported_csr_mask[uvma_core_cntrl_pkg::MSTATUSH] = 0; - unsupported_csr_mask[uvma_core_cntrl_pkg::CYCLE] = 0; - unsupported_csr_mask[uvma_core_cntrl_pkg::INSTRET] = 0; - unsupported_csr_mask[uvma_core_cntrl_pkg::CYCLEH] = 0; - unsupported_csr_mask[uvma_core_cntrl_pkg::INSTRETH] = 0; + // Zihpm extension CSRs + if (ext_zihpm_supported) begin + for (int i = 0; i < MAX_NUM_HPMCOUNTERS; i++) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::HPMCOUNTER3+i] = 0; + if (xlen == 32) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::HPMCOUNTER3H+i] = 0; + end + else if (xlen ==64) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::HPMCOUNTER3H+i] = 1; + end + end + end + else begin + for (int i = 0; i < MAX_NUM_HPMCOUNTERS; i++) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::HPMCOUNTER3+i] = 1; + unsupported_csr_mask[uvma_core_cntrl_pkg::HPMCOUNTER3H+i] = 1; + end + end + + // Upper Machine mode CSRs + if (xlen == 32) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::MSTATUSH] = 0; + unsupported_csr_mask[uvma_core_cntrl_pkg::MCYCLEH] = 0; + unsupported_csr_mask[uvma_core_cntrl_pkg::MINSTRETH] = 0; + end + else if (xlen == 64) begin + unsupported_csr_mask[uvma_core_cntrl_pkg::MSTATUSH] = 1; + unsupported_csr_mask[uvma_core_cntrl_pkg::MCYCLEH] = 1; + unsupported_csr_mask[uvma_core_cntrl_pkg::MINSTRETH] = 1; + end // Remove unsupported pmp CSRs if (nr_pmp_entries == 0) begin diff --git a/verif/sim/cva6.hvp b/verif/sim/cva6.hvp index d74e50237..7034b2908 100644 --- a/verif/sim/cva6.hvp +++ b/verif/sim/cva6.hvp @@ -725,34 +725,14 @@ plan "CVA6 Verification Master Plan"; endfeature feature "CSR access"; description = "CSR registers access.\nSpecification: Done, Dvplan: Done, Verification execution: Done"; - feature CYCLE; - measure Group CYCLE; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.cycle.cycle__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.cycle.cycle__write_cg"; - endmeasure - endfeature - feature CYCLEH; - measure Group CYCLEH; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.cycleh.cycleh__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.cycleh.cycleh__write_cg"; - endmeasure - endfeature feature ICACHE; measure Group ICACHE; source = "group instance: uvme_cva6_pkg.csr_reg_cov.icache.icache__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.icache.icache__write_cg"; endmeasure endfeature - feature INSTRET; - measure Group INSTRET; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.instret.instret__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.instret.instret__write_cg"; - endmeasure - endfeature - feature INSTRETH; - measure Group INSTRETH; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.instreth.instreth__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.instreth.instreth__write_cg"; - endmeasure - endfeature feature MARCHID; measure Group MARCHID; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.marchid.marchid__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.marchid.marchid__write_cg"; + source = "group instance: uvme_cva6_pkg.csr_reg_cov.marchid.marchid__read_cg"; endmeasure endfeature feature MCAUSE; @@ -767,7 +747,7 @@ plan "CVA6 Verification Master Plan"; endfeature feature MHARTID; measure Group MHARTID; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.mhartid.mhartid__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.mhartid.mhartid__write_cg"; + source = "group instance: uvme_cva6_pkg.csr_reg_cov.mhartid.mhartid__read_cg"; endmeasure endfeature feature MIE; @@ -777,7 +757,7 @@ plan "CVA6 Verification Master Plan"; endfeature feature MIMPID; measure Group MIMPID; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.mimpid.mimpid__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.mimpid.mimpid__write_cg"; + source = "group instance: uvme_cva6_pkg.csr_reg_cov.mimpid.mimpid__read_cg"; endmeasure endfeature feature MIP; @@ -817,7 +797,7 @@ plan "CVA6 Verification Master Plan"; endfeature feature MVENDORID; measure Group MVENDORID; - source = "group instance: uvme_cva6_pkg.csr_reg_cov.mvendorid.mvendorid__read_cg", "group instance: uvme_cva6_pkg.csr_reg_cov.mvendorid.mvendorid__write_cg"; + source = "group instance: uvme_cva6_pkg.csr_reg_cov.mvendorid.mvendorid__read_cg"; endmeasure endfeature feature PMPADDR0; diff --git a/verif/tests/custom/csr_embedded/csr_counters_overflow.S b/verif/tests/custom/csr_embedded/csr_counters_overflow.S index 02bec108d..6e7762a3b 100644 --- a/verif/tests/custom/csr_embedded/csr_counters_overflow.S +++ b/verif/tests/custom/csr_embedded/csr_counters_overflow.S @@ -19,8 +19,6 @@ csr_cycle_overflow: csrw mcycle, x3 #Read backs registers - csrr x14, cycle - csrr x14, cycleh csrr x14, mcycle csrr x14, mcycleh @@ -35,8 +33,6 @@ csr_cycle_overflow: nop #Read backs registers. cycle and mcycle should be arround 0, cycleh and mcycleh should increment by 1 - csrr x14, cycle - csrr x14, cycleh csrr x14, mcycle csrr x14, mcycleh @@ -47,8 +43,6 @@ csr_cycle_overflow: csrw mcycle, x3 #Read backs registers - csrr x14, cycle - csrr x14, cycleh csrr x14, mcycle csrr x14, mcycleh @@ -63,8 +57,6 @@ csr_cycle_overflow: nop #Read backs registers, cycle and mcycle should be arround 0, cycleh and mcycleh should be 0 - csrr x14, cycle - csrr x14, cycleh csrr x14, mcycle csrr x14, mcycleh @@ -76,8 +68,6 @@ csr_instert_overflow: csrw minstret, x3 #Read backs registers - csrr x14, instret - csrr x14, instreth csrr x14, minstret csrr x14, minstreth @@ -100,8 +90,6 @@ csr_instert_overflow: nop #Read backs registers. instret and minstret should be arround 0, instreth and minstreth should increment by 1 - csrr x14, instret - csrr x14, instreth csrr x14, minstret csrr x14, minstreth @@ -112,8 +100,6 @@ csr_instert_overflow: csrw minstret, x3 #Read backs registers - csrr x14, instret - csrr x14, instreth csrr x14, minstret csrr x14, minstreth @@ -136,8 +122,6 @@ csr_instert_overflow: nop #Read backs registers, instret and minstret should be arround 0, instreth and minstreth should be 0 - csrr x14, instret - csrr x14, instreth csrr x14, minstret csrr x14, minstreth diff --git a/verif/tests/custom/csr_embedded/csrcs_test.S b/verif/tests/custom/csr_embedded/csrcs_test.S index 3d26b2a49..4a45be9ab 100644 --- a/verif/tests/custom/csr_embedded/csrcs_test.S +++ b/verif/tests/custom/csr_embedded/csrcs_test.S @@ -10,6 +10,54 @@ csrcs: #Start CSR tests: Write/Read all RW registers registers in a random order using Clear/Set instructions #User ignored registers: + ########################## + #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16} + ########################## + #MTVAL Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x343, x3 + li x3, 0x1f + csrrs x14, 0x343, x3 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x343, x3 + li x3, 0x0 + csrrs x14, 0x343, x3 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x343, x3 + li x3, 0x15 + csrrs x14, 0x343, x3 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x343, x3 + li x3, 0xa + csrrs x14, 0x343, x3 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x16 + li x3, 0xffffffe9 + csrrc x14, 0x343, x3 + li x3, 0x16 + csrrs x14, 0x343, x3 + + #MTVAL read value + csrr x14, 0x343 + ########################## #MHPMEVENT22 testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16} ########################## diff --git a/verif/tests/custom/csr_embedded/csrcsi_test.S b/verif/tests/custom/csr_embedded/csrcsi_test.S index 9c4775b1a..713339d46 100644 --- a/verif/tests/custom/csr_embedded/csrcsi_test.S +++ b/verif/tests/custom/csr_embedded/csrcsi_test.S @@ -10,6 +10,44 @@ csrcsi: #Start CSR tests: Write/Read all RW registers in a random order using Clear/Set immediate instructions #User ignored registers: + ########################## + #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hb} + ########################## + #MTVAL Write clear/set value 0x1f + csrrci x14, 0x343, 0x0 + csrrsi x14, 0x343, 0x1f + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x0 + csrrci x14, 0x343, 0x1f + csrrsi x14, 0x343, 0x0 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x15 + csrrci x14, 0x343, 0xa + csrrsi x14, 0x343, 0x15 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0xa + csrrci x14, 0x343, 0x15 + csrrsi x14, 0x343, 0xa + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write clear/set value 0xb + csrrci x14, 0x343, 0x14 + csrrsi x14, 0x343, 0xb + + #MTVAL read value + csrr x14, 0x343 + ########################## #MHPMCOUNTER23 testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hb} ########################## diff --git a/verif/tests/custom/csr_embedded/csrrst_test.S b/verif/tests/custom/csr_embedded/csrrst_test.S index d74b45bc4..92d6ff1be 100644 --- a/verif/tests/custom/csr_embedded/csrrst_test.S +++ b/verif/tests/custom/csr_embedded/csrrst_test.S @@ -34,9 +34,6 @@ csrrst: #MHPMEVENT28 read value csrr x14, 0x33c - #INSTRETH read value - csrr x14, 0xc82 - #MHPMCOUNTERH9 read value csrr x14, 0xb89 @@ -85,9 +82,6 @@ csrrst: #MHPMCOUNTER13 read value csrr x14, 0xb0d - #INSTRET read value - csrr x14, 0xc02 - #MHPMCOUNTERH19 read value csrr x14, 0xb93 @@ -115,9 +109,6 @@ csrrst: #MHPMCOUNTERH15 read value csrr x14, 0xb8f - #CYCLE read value - csrr x14, 0xc00 - #MHPMEVENT27 read value csrr x14, 0x33b @@ -181,9 +172,6 @@ csrrst: #MHPMEVENT17 read value csrr x14, 0x331 - #CYCLEH read value - csrr x14, 0xc80 - #PMPADDR10 read value csrr x14, 0x3ba diff --git a/verif/tests/custom/csr_embedded/csrrw_test.S b/verif/tests/custom/csr_embedded/csrrw_test.S index e50aadfcc..62581f9fd 100644 --- a/verif/tests/custom/csr_embedded/csrrw_test.S +++ b/verif/tests/custom/csr_embedded/csrrw_test.S @@ -3984,6 +3984,44 @@ csrrw: #CYCLE WR skipped since it's a RO register + ########################## + #MTVAL testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h162b0d42} + ########################## + #MTVAL Write value 0xffffffff + li x3, 0xffffffff + csrw 0X343, x3 + + #MTVAL read value + csrr x14, 0X343 + + #MTVAL Write value 0x0 + li x3, 0x0 + csrw 0X343, x3 + + #MTVAL read value + csrr x14, 0X343 + + #MTVAL Write value 0x55555555 + li x3, 0x55555555 + csrw 0X343, x3 + + #MTVAL read value + csrr x14, 0X343 + + #MTVAL Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0X343, x3 + + #MTVAL read value + csrr x14, 0X343 + + #MTVAL Write value 0x162b0d42 + li x3, 0x162b0d42 + csrw 0X343, x3 + + #MTVAL read value + csrr x14, 0X343 + ########################## #MHPMCOUNTERH10 testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h162b0d42} ########################## diff --git a/verif/tests/custom/csr_embedded/csrrwi_test.S b/verif/tests/custom/csr_embedded/csrrwi_test.S index c8b46ff77..5ada699db 100644 --- a/verif/tests/custom/csr_embedded/csrrwi_test.S +++ b/verif/tests/custom/csr_embedded/csrrwi_test.S @@ -308,7 +308,7 @@ csrrwi: csrr x14, 0x3bc ########################## - #PMPADDR11 testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16} + #PMPADDR11 testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16} ########################## #PMPADDR11 Write immediate value 0x1f csrrwi x14, 0x3bb, 0x1f @@ -340,6 +340,39 @@ csrrwi: #PMPADDR11 read value csrr x14, 0x3bb + ########################## + #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18} + ########################## + #MTVAL Write immediate value 0x1f + csrrwi x14, 0x343, 0x1f + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write immediate value 0x0 + csrrwi x14, 0x343, 0x0 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write immediate value 0x15 + csrrwi x14, 0x343, 0x15 + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write immediate value 0xa + csrrwi x14, 0x343, 0xa + + #MTVAL read value + csrr x14, 0x343 + + #MTVAL Write immediate value 0x18 + csrrwi x14, 0x343, 0x18 + + #MTVAL read value + csrr x14, 0x343 + ########################## #MHPMCOUNTERH11 testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18} ##########################