diff --git a/Makefile b/Makefile
index df3a0eccc..505caba5f 100644
--- a/Makefile
+++ b/Makefile
@@ -52,7 +52,9 @@ riscv-tests =  rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-
 			   rv64ui-v-sraiw rv64ui-v-sraw rv64ui-v-srl rv64ui-v-srli rv64ui-v-srliw rv64ui-v-srlw \
 			   rv64ui-v-lb rv64ui-v-lbu rv64ui-v-ld rv64ui-v-lh rv64ui-v-lhu rv64ui-v-lui
 
-
+# failed test directory
+failed-tests =  $(wildcard failedtests/*.S)
+# preset which runs a single test
 riscv-test = rv64ui-p-add
 # Search here for include files (e.g.: non-standalone components)
 incdir = ./includes
@@ -112,13 +114,23 @@ $(library):
 	vlib${questa_version} ${library}
 
 sim: build
-	vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
+	vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) \
+	+ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
 
 simc: build
-	vsim${questa_version} -c -lib ${library} ${top_level}_optimized +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
+	vsim${questa_version} -c -lib ${library} ${top_level}_optimized +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+	 +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
 
 run-asm-tests: build
-	$(foreach test, $(riscv-tests), vsim$(questa_version) +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $(library).$(test_top_level)_optimized;)
+	$(foreach test, $(riscv-tests), vsim$(questa_version) +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles)
+		+UVM_TESTNAME=$(test_case) +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c \
+		-coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS \
+		-concise]" $(library).$(test_top_level)_optimized;)
+
+run-failed-tests: build
+	cd failedtests && make
+	$(foreach test, $(failed-tests:.S=), vsim$(questa_version) -c -lib ${library} $(top_level)_optimized \
+		+max-cycles=$(max_cycles) +UVM_TESTNAME=$(test) +BASEDIR=. +ASMTEST=$(test))
 
 # Run the specified test case
 $(tests): build
diff --git a/failedtests/.gitignore b/failedtests/.gitignore
new file mode 100644
index 000000000..f7b9a6d49
--- /dev/null
+++ b/failedtests/.gitignore
@@ -0,0 +1,8 @@
+# Ignore all
+*
+# Unignore all with extensions
+!*.*
+# Ignore files with specific extension
+*.hex
+*.dump
+*.sig
diff --git a/failedtests/Makefile b/failedtests/Makefile
new file mode 100644
index 000000000..b01637228
--- /dev/null
+++ b/failedtests/Makefile
@@ -0,0 +1,72 @@
+#=======================================================================
+# UCB VLSI FLOW: Makefile for riscv-tests
+#-----------------------------------------------------------------------
+# Yunsup Lee (yunsup@cs.berkeley.edu)
+#
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+asm_tests =  $(wildcard *.S)
+
+extra_files =
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv64-unknown-elf-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=rv64i
+RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
+RISCV_OBJDUMP = riscv64-unknown-elf-objdump --disassemble-all --section=.text --section=.data --section=.bss
+RISCV_SIM = spike
+
+#------------------------------------------------------------
+# Build assembly tests
+
+asm_tests_bin     = $(patsubst %.S, %, $(asm_tests))
+asm_tests_verilog = $(addsuffix .v,    $(asm_tests_bin))
+asm_tests_dump    = $(addsuffix .dump, $(asm_tests_bin))
+asm_tests_sig     = $(addsuffix .sig,  $(asm_tests_bin))
+asm_tests_hex     = $(addsuffix .hex,  $(asm_tests_bin))
+
+$(asm_tests_dump): %.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+$(asm_tests_verilog): %.v: %
+	$(RISCV_OBJCOPY) -O verilog $< $@
+
+$(asm_tests_bin): %: %.S $(extra_files)
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../riscv-torture/env/p -T../riscv-torture/env/p/link.ld $< -o $@
+
+$(asm_tests_hex): %.hex: % $(extra_files)
+	elf2hex 8 16384 $< 2147483648 > $@
+
+$(asm_tests_sig): %.sig: %
+	$(RISCV_SIM) +signature=$@ $<
+
+new:
+	cd ..; make gen
+
+run: $(asm_tests_sig)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(asm_tests_sig); echo;
+
+junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) $(asm_tests_hex)
+
+#------------------------------------------------------------
+# Default
+
+all: $(asm_tests_dump) $(asm_tests_hex)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
+
+clean-all: clean
+	rm -rf test*.S test*.stats test*.hex test*.out test*.dump test test_1* test_pseg_* schad* failedtests/*