diff --git a/ariane-run-torture b/ariane-run-torture
new file mode 100755
index 000000000..0bc5d8cab
--- /dev/null
+++ b/ariane-run-torture
@@ -0,0 +1,8 @@
+#!/bin/sh
+# make the verilog first
+cd output && make
+cd ../..
+# start the simulation
+vsim-10.6 -c -lib work core_tb_optimized +UVM_TESTNAME=core_test $2 +ASMTEST=riscv-torture/$3 -coverage -classdebug -do "run -a"
+# move the signature file to the appropriate place
+mv test.ariane.sig riscv-torture/output/test.rtlsim.sig
diff --git a/riscv-torture b/riscv-torture
index 57d94cc21..06e613373 160000
--- a/riscv-torture
+++ b/riscv-torture
@@ -1 +1 @@
-Subproject commit 57d94cc210379aa75ac9705aa1e424877aa2c9c5
+Subproject commit 06e613373596d04ca790e5e3b07894f3eae063df