diff --git a/core/cva6.sv b/core/cva6.sv index b06ccd128..4502b60b0 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1533,9 +1533,7 @@ module cva6 // Parameter Check // ------------------- // pragma translate_off -`ifndef VERILATOR initial config_pkg::check_cfg(CVA6Cfg); -`endif // pragma translate_on // ------------------- diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index 4a9a56086..d1d7e2116 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -209,7 +209,6 @@ module cva6_fifo_v3 #( end // pragma translate_off -`ifndef VERILATOR initial begin assert (DEPTH > 0) else $error("DEPTH must be greater than 0."); @@ -222,7 +221,6 @@ module cva6_fifo_v3 #( empty_read : assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i)) else $fatal(1, "Trying to pop data although the FIFO is empty."); -`endif // pragma translate_on endmodule // fifo_v3 diff --git a/core/cva6_mmu/cva6_tlb.sv b/core/cva6_mmu/cva6_tlb.sv index 522004d3e..68083f3e2 100644 --- a/core/cva6_mmu/cva6_tlb.sv +++ b/core/cva6_mmu/cva6_tlb.sv @@ -400,7 +400,6 @@ for ( //-------------- //pragma translate_off -`ifndef VERILATOR initial begin : p_assertions assert ((TLB_ENTRIES % 2 == 0) && (TLB_ENTRIES > 1)) @@ -435,7 +434,6 @@ for ( $stop(); end -`endif //pragma translate_on endmodule diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 3117e2765..97360a3b8 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -575,12 +575,4 @@ module frontend .fetch_entry_ready_i(fetch_entry_ready_i) // to back-end ); - // pragma translate_off -`ifndef VERILATOR - initial begin - assert (CVA6Cfg.FETCH_WIDTH == 32 || CVA6Cfg.FETCH_WIDTH == 64) - else $fatal(1, "[frontend] fetch width != not supported"); - end -`endif - // pragma translate_on endmodule diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index ceac06bbe..28254e470 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -551,7 +551,6 @@ module instr_queue end // pragma translate_off -`ifndef VERILATOR replay_address_fifo : assert property (@(posedge clk_i) disable iff (!rst_ni) replay_o |-> !i_fifo_address.push_i) else $fatal(1, "[instr_queue] Pushing address although replay asserted"); @@ -562,6 +561,5 @@ module instr_queue $error("Output select should be one-hot encoded"); $stop(); end -`endif // pragma translate_on endmodule diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 6319642c5..8e3b87db8 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -369,7 +369,6 @@ package config_pkg; /// sense for all parameters, here is the place to sanity check them. function automatic void check_cfg(cva6_cfg_t Cfg); // pragma translate_off -`ifndef VERILATOR assert (Cfg.RASDepth > 0); assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries)); assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries)); @@ -379,7 +378,8 @@ package config_pkg; assert (Cfg.NrPMPEntries <= 64); assert (!(Cfg.SuperscalarEn && Cfg.RVF)); assert (!(Cfg.SuperscalarEn && Cfg.RVZCMP)); -`endif + assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64) + else $fatal(1, "[frontend] fetch width != not supported"); // pragma translate_on endfunction diff --git a/core/load_unit.sv b/core/load_unit.sv index 2109b08de..0a66c5106 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -546,7 +546,6 @@ module load_unit /////////////////////////////////////////////////////// //pragma translate_off -`ifndef VERILATOR initial assert (CVA6Cfg.DcacheIdWidth >= REQ_ID_BITS) else $fatal(1, "DcacheIdWidth parameter is not wide enough to encode pending loads"); @@ -563,7 +562,6 @@ module load_unit assert property (@(posedge clk_i) disable iff (~rst_ni) ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> ldbuf_wdata.address_offset < 8) else $fatal(1, "invalid address offset used with {LB, LBU}"); -`endif //pragma translate_on endmodule