diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index 3fea75594..f162beb9f 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -2570,10 +2570,11 @@ module csr_regfile
                                priv_lvl_o != riscv::PRIV_LVL_M && v_q)
                               ? 1'b1
                               : 1'b0;
+  end else if (CVA6Cfg.RVS) begin
+    assign en_translation_o   = (satp_mode_is_sv && priv_lvl_o != riscv::PRIV_LVL_M) ? 1'b1 : 1'b0;
+    assign en_g_translation_o = 1'b0;
   end else begin
-    assign en_translation_o = (satp_mode_is_sv && priv_lvl_o != riscv::PRIV_LVL_M)
-                             ? 1'b1
-                             : 1'b0;
+    assign en_translation_o   = 1'b0;
     assign en_g_translation_o = 1'b0;
   end
   assign mxr_o  = mstatus_q.mxr;