diff --git a/src/branch_unit.sv b/src/branch_unit.sv
index bbbe630f6..4471d6bd8 100644
--- a/src/branch_unit.sv
+++ b/src/branch_unit.sv
@@ -115,8 +115,12 @@ module branch_unit (
             if (target_address[0] == 1'b0) begin
                 // we've got a valid branch prediction
                 if (branch_predict_i.valid) begin
-                    // if the address or the outcome don't match we've got a mis-predict
-                    if (target_address != branch_predict_i.predict_address || branch_predict_i.predict_taken != comparison_result) begin
+                    // if the outcome doesn't match we've got a mis-predict
+                    if (branch_predict_i.predict_taken != comparison_result) begin
+                        resolved_branch_o.is_mispredict  = 1'b1;
+                    end
+                    // check if the address of the predict taken branch is correct
+                    if (branch_predict_i.predict_taken && target_address != branch_predict_i.predict_address) begin
                         resolved_branch_o.is_mispredict  = 1'b1;
                     end
                 // branch-prediction didn't do anything (e.g.: it fetched PC + 2/4), so if this branch is taken
diff --git a/src/lsu.sv b/src/lsu.sv
index 8535ca4a0..3a3845d51 100644
--- a/src/lsu.sv
+++ b/src/lsu.sv
@@ -84,6 +84,7 @@ module lsu #(
     // --------------------------------------
     // those are the signals which are always correct
     // e.g.: they keep the value in the stall case
+    logic                     valid;
     logic [63:0]              vaddr;
     logic [63:0]              data;
     logic [7:0]               be;
@@ -91,6 +92,7 @@ module lsu #(
     fu_op                     operator;
     logic [TRANS_ID_BITS-1:0] trans_id;
     // registered address in case of a necessary stall
+    logic                     valid_n,    valid_q;
     logic [63:0]              vaddr_n,    vaddr_q;
     logic [63:0]              data_n,     data_q;
     fu_t                      fu_n,       fu_q;
@@ -339,9 +341,9 @@ module lsu #(
         // check the operator to activate the right functional unit accordingly
         unique case (fu)
             // all loads go here
-            LOAD:  ld_valid_i = lsu_valid_i;
+            LOAD:  ld_valid_i = valid;
             // all stores go here
-            STORE: st_valid_i = lsu_valid_i;
+            STORE: st_valid_i = valid;
             // not relevant for the LSU
             default: ;
         endcase
@@ -459,6 +461,7 @@ module lsu #(
     always_comb begin : input_select
         // if we are stalling use the values we saved
         if (stall_q) begin
+            valid     = valid_q;
             vaddr     = vaddr_q;
             data      = data_q;
             fu        = fu_q;
@@ -466,6 +469,7 @@ module lsu #(
             trans_id  = trans_id_q;
             be        = be_q;
         end else begin // otherwise bypass them
+            valid     = lsu_valid_i;
             vaddr     = vaddr_i;
             data      = operand_b_i;
             fu        = fu_i;
@@ -476,6 +480,7 @@ module lsu #(
     end
     // 1st register stage
     always_comb begin : register_stage
+        valid_n     = valid_q;
         vaddr_n     = vaddr_q;
         data_n      = data_q;
         fu_n        = fu_q;
@@ -484,12 +489,13 @@ module lsu #(
         be_n        = be_q;
         // get new input data
         if (lsu_valid_i) begin
-             vaddr_n     = vaddr_i;
-             data_n      = operand_b_i;
-             fu_n        = fu_i;
-             operator_n  = operator_i;
-             trans_id_n  = trans_id_i;
-             be_n        = be_i;
+            valid_n     = lsu_valid_i;
+            vaddr_n     = vaddr_i;
+            data_n      = operand_b_i;
+            fu_n        = fu_i;
+            operator_n  = operator_i;
+            trans_id_n  = trans_id_i;
+            be_n        = be_i;
         end
 
         if (lsu_ready_o) begin
@@ -503,6 +509,7 @@ module lsu #(
     always_ff @(posedge clk_i or negedge rst_ni) begin
         if (~rst_ni) begin
             // 1st LSU stage
+            valid_q             <= 1'b0;
             vaddr_q             <= 64'b0;
             data_q              <= 64'b0;
             fu_q                <= NONE;
@@ -512,6 +519,7 @@ module lsu #(
             stall_q             <= 1'b0;
         end else begin
             // 1st LSU stage
+            valid_q             <= valid_n;
             vaddr_q             <= vaddr_n;
             data_q              <= data_n;
             fu_q                <= fu_n;
diff --git a/src/scoreboard.sv b/src/scoreboard.sv
index 7c79e4ff0..c99b72cd5 100644
--- a/src/scoreboard.sv
+++ b/src/scoreboard.sv
@@ -109,16 +109,6 @@ module scoreboard #(
             issue_pointer_n = issue_pointer_q + 1'b1;
         end
 
-        // we've got an acknowledge from commit
-        if (commit_ack_i) begin
-            // decrease the issue counter
-            issue_cnt--;
-            // this instruction is no longer in issue e.g.: it is considered finished
-            mem_n[commit_pointer_q].issued    = 1'b0;
-            mem_n[commit_pointer_q].sbe.valid = 1'b0;
-            // advance commit pointer
-            commit_pointer_n = commit_pointer_n + 1'b1;
-        end
         // ------------
         // Write Back
         // ------------
@@ -132,6 +122,19 @@ module scoreboard #(
             end
         end
 
+        // ------------
+        // Commit Port
+        // ------------
+        // we've got an acknowledge from commit
+        if (commit_ack_i) begin
+            // decrease the issue counter
+            issue_cnt--;
+            // this instruction is no longer in issue e.g.: it is considered finished
+            mem_n[commit_pointer_q].issued    = 1'b0;
+            mem_n[commit_pointer_q].sbe.valid = 1'b0;
+            // advance commit pointer
+            commit_pointer_n = commit_pointer_n + 1'b1;
+        end
         // ------
         // Flush
         // ------