diff --git a/Makefile b/Makefile
index 6d4db7c51..a302cc41d 100755
--- a/Makefile
+++ b/Makefile
@@ -112,7 +112,7 @@ $(library):
 # +jtag_rbb_enable=1
 sim: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug  \
+	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug  +jtag_rbb_enable=1 \
 	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
 
 simc: build $(library)/ariane_dpi.so
diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv
index ecd09cf22..b3b726f25 100644
--- a/src/csr_regfile.sv
+++ b/src/csr_regfile.sv
@@ -832,7 +832,7 @@ module csr_regfile #(
             // machine mode registers
             mstatus_q              <= 64'b0;
             // set to boot address + direct mode + 4 byte offset which is the initial trap
-            mtvec_q                <= {boot_addr_i[63:3], 3'h4};
+            mtvec_q                <= boot_addr_i + 'h40;
             medeleg_q              <= 64'b0;
             mideleg_q              <= 64'b0;
             mip_q                  <= 64'b0;