From 38f44dad7cc0ad7cd28f81c9b9eb154b33184596 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?=
 <61976467+ASintzoff@users.noreply.github.com>
Date: Fri, 21 Mar 2025 14:56:44 +0100
Subject: [PATCH] csr_regfile.sv: use better signal name (CSR_MTVEC) (#2854)

Vectored instead of misleading DirVecOnly
---
 core/csr_regfile.sv | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index 3a409d592..e80b7005a 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -1473,12 +1473,13 @@ module csr_regfile
         end
 
         riscv::CSR_MTVEC: begin
-          logic DirVecOnly;
-          DirVecOnly = CVA6Cfg.DirectVecOnly ? 1'b0 : csr_wdata[0];
-          mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, DirVecOnly};
+          logic Vectored;
+          Vectored = CVA6Cfg.DirectVecOnly ? 1'b0 : csr_wdata[0];
+          if (!Vectored) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, Vectored};
           // we are in vector mode, this implementation requires the additional
           // alignment constraint of 64 * 4 bytes
-          if (DirVecOnly) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, DirVecOnly};
+          else
+            mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, Vectored};
         end
         riscv::CSR_MCOUNTEREN: begin
           if (CVA6Cfg.RVU) mcounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]};