diff --git a/Makefile b/Makefile index bdc720eab..a0d89f23f 100755 --- a/Makefile +++ b/Makefile @@ -43,16 +43,6 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \ dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc)) dpi_hdr := $(wildcard tb/dpi/*.h) # this list contains the standalone components -# <<<<<<< HEAD -# src := $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard src/axi_slice/*.sv) \ -# $(wildcard src/axi_node/*.sv) $(wildcard src/axi_mem_if/src/*.sv) src/fpu_legacy/hdl/fpu_utils/fpu_ff.sv \ -# src/fpu_legacy/hdl/fpu_div_sqrt_mvp/defs_div_sqrt_mvp.sv $(wildcard src/fpu_legacy/hdl/fpu_div_sqrt_mvp/*.sv) \ -# $(fpnew_pkg) $(wildcard src/fpnew/src/utils/*.vhd) $(wildcard src/fpnew/src/ops/*.vhd) \ -# $(wildcard src/fpnew/src/subunits/*.vhd) src/fpnew/src/fpnew.vhd src/fpnew/src/fpnew_top.vhd \ -# $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) $(wildcard bootrom/*.sv) \ -# $(wildcard src/debug/debug_rom/*.sv) - -# ======= src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ $(wildcard src/fpu/src/utils/*.vhd) \ $(wildcard src/fpu/src/ops/*.vhd) \ @@ -160,7 +150,7 @@ $(riscv-asm-tests): build $(library)/ariane_dpi.so +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ $(QUESTASIM_FLAGS) \ -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \ - -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ + -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log $(riscv-benchmarks): build $(library)/ariane_dpi.so @@ -168,7 +158,7 @@ $(riscv-benchmarks): build $(library)/ariane_dpi.so +BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ $(QUESTASIM_FLAGS) \ -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \ - -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ + -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ ${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log diff --git a/ci/riscv-asm-tests.list b/ci/riscv-asm-tests.list index aeb1b746d..144584d3a 100644 --- a/ci/riscv-asm-tests.list +++ b/ci/riscv-asm-tests.list @@ -149,3 +149,19 @@ rv64uf-v-fmin rv64uf-v-ldst rv64uf-v-move rv64uf-v-recoding +rv64ud-p-fadd +rv64ud-p-fclass +rv64ud-p-fcmp +rv64ud-p-fcvt +rv64ud-p-fcvt_w +rv64ud-p-fdiv +rv64ud-p-fmadd +rv64ud-p-fmin +rv64ud-v-fadd +rv64ud-v-fclass +rv64ud-v-fcmp +rv64ud-v-fcvt +rv64ud-v-fcvt_w +rv64ud-v-fdiv +rv64ud-v-fmadd +rv64ud-v-fmin diff --git a/src/ariane.sv b/src/ariane.sv index edaff22fa..4d4178a70 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -367,11 +367,11 @@ module ariane #( .lsu_exception_o ( lsu_exception_ex_id ), .no_st_pending_o ( no_st_pending_ex_commit ), // MULT - // .mult_ready_o ( mult_ready_ex_id ), - // .mult_valid_i ( mult_valid_id_ex ), - // .mult_trans_id_o ( mult_trans_id_ex_id ), - // .mult_result_o ( mult_result_ex_id ), - // .mult_valid_o ( mult_valid_ex_id ), + .mult_ready_o ( mult_ready_ex_id ), + .mult_valid_i ( mult_valid_id_ex ), + .mult_trans_id_o ( mult_trans_id_ex_id ), + .mult_result_o ( mult_result_ex_id ), + .mult_valid_o ( mult_valid_ex_id ), // FPU .fpu_ready_o ( fpu_ready_ex_id ), .fpu_valid_i ( fpu_valid_id_ex ), @@ -405,12 +405,6 @@ module ariane #( .asid_i ( asid_csr_ex ), // from CSR .icache_areq_i ( icache_areq_cache_ex ), .icache_areq_o ( icache_areq_ex_cache ), - - .mult_ready_o ( mult_ready_ex_id ), - .mult_valid_i ( mult_valid_id_ex ), - .mult_trans_id_o ( mult_trans_id_ex_id ), - .mult_result_o ( mult_result_ex_id ), - .mult_valid_o ( mult_valid_ex_id ), // DCACHE interfaces .dcache_req_ports_i ( dcache_req_ports_cache_ex ), .dcache_req_ports_o ( dcache_req_ports_ex_cache ) diff --git a/src/load_unit.sv b/src/load_unit.sv index bef553255..2a4cdc462 100644 --- a/src/load_unit.sv +++ b/src/load_unit.sv @@ -331,8 +331,8 @@ module load_unit ( // prepare these signals for faster selection in the next cycle - assign signed_d = load_data_q.operator inside { LW, LH, LB }; - assign fp_sign_d = load_data_q.operator inside { FLW, FLH, FLB }; + assign signed_d = load_data_d.operator inside {LW, LH, LB}; + assign fp_sign_d = load_data_d.operator inside {FLW, FLH, FLB}; assign idx_d = (load_data_d.operator inside {LW, FLW}) ? load_data_d.address_offset + 3 : (load_data_d.operator inside {LH, FLH}) ? load_data_d.address_offset + 1 : load_data_d.address_offset; @@ -354,15 +354,15 @@ module load_unit ( // result mux always_comb begin unique case (load_data_q.operator) - LW, LWU: result_o = {{32{sign_bit}}, shifted_data[31:0]}; - LH, LHU: result_o = {{48{sign_bit}}, shifted_data[15:0]}; - LB, LBU: result_o = {{56{sign_bit}}, shifted_data[7:0]}; + LW, LWU, FLW: result_o = {{32{sign_bit}}, shifted_data[31:0]}; + LH, LHU, FLH: result_o = {{48{sign_bit}}, shifted_data[15:0]}; + LB, LBU, FLB: result_o = {{56{sign_bit}}, shifted_data[7:0]}; default: result_o = shifted_data; endcase end always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if(~rst_ni) begin + if (~rst_ni) begin idx_q <= 0; signed_q <= 0; fp_sign_q <= 0; diff --git a/tb/wave/wave_core.do b/tb/wave/wave_core.do index 8e74fc121..53caa9d0c 100644 --- a/tb/wave/wave_core.do +++ b/tb/wave/wave_core.do @@ -5,8 +5,8 @@ add wave -noupdate -group frontend -group icache /ariane_tb/dut/i_ariane/i_std_c add wave -noupdate -group frontend -group ras /ariane_tb/dut/i_ariane/i_frontend/i_ras/* add wave -noupdate -group frontend -group btb /ariane_tb/dut/i_ariane/i_frontend/i_btb/* add wave -noupdate -group frontend -group bht /ariane_tb/dut/i_ariane/i_frontend/i_bht/* -add wave -noupdate -group frontend -group instr_scan /ariane_tb/dut/i_ariane/i_frontend/*/i_instr_scan/* -add wave -noupdate -group frontend -group fetch_fifo /ariane_tb/dut/i_ariane/i_frontend/i_fetch_fifo/* +# add wave -noupdate -group frontend -group instr_scan /ariane_tb/dut/i_ariane/i_frontend/*/i_instr_scan/* +# add wave -noupdate -group frontend -group fetch_fifo /ariane_tb/dut/i_ariane/i_frontend/i_fetch_fifo/* add wave -noupdate -group id_stage -group decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/* add wave -noupdate -group id_stage -group compressed_decoder /ariane_tb/dut/i_ariane/id_stage_i/compressed_decoder_i/* @@ -22,6 +22,8 @@ add wave -noupdate -group ex_stage -group alu /ariane_tb/dut/i_ariane/ex_stage_i add wave -noupdate -group ex_stage -group mult /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/* add wave -noupdate -group ex_stage -group mult -group mul /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/i_mul/* add wave -noupdate -group ex_stage -group mult -group div /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/i_div/* +add wave -noupdate -group ex_stage -group fpu /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/* +add wave -noupdate -group ex_stage -group fpu -group fpnew /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/* add wave -noupdate -group ex_stage -group lsu /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/* add wave -noupdate -group ex_stage -group lsu -group lsu_bypass /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/lsu_bypass_i/*