diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index 1cec07ca2..c48507658 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -1,2 +1,2 @@ cv32a65x: - gates: 185674 + gates: 184701 diff --git a/core/branch_unit.sv b/core/branch_unit.sv index 068883663..074eb502f 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -58,7 +58,6 @@ module branch_unit #( // TODO(zarubaf): The ALU can be used to calculate the branch target jump_base = (fu_data_i.operation == ariane_pkg::JALR) ? fu_data_i.operand_a[CVA6Cfg.VLEN-1:0] : pc_i; - target_address = {CVA6Cfg.VLEN{1'b0}}; resolve_branch_o = 1'b0; resolved_branch_o.target_address = {CVA6Cfg.VLEN{1'b0}}; resolved_branch_o.is_taken = 1'b0; diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 8984b7d62..b717f785a 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -115,9 +115,8 @@ module commit_stage for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( commit_instr_i[i].op - ))); - // Check if we issued a vector floating-point instruction to the accellerator - dirty_fp_state_o |= commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp; + // Check if we issued a vector floating-point instruction to the accellerator + ))) | commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp; end end diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index acb6986c4..0e8f851c8 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -886,7 +886,7 @@ module csr_regfile // -------------------- cycle_d = cycle_q; instret_d = instret_q; - if (!debug_mode_q) begin + if (!(CVA6Cfg.DebugEn && debug_mode_q)) begin // increase instruction retired counter for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin if (commit_ack_i[i] && !ex_i.valid && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2]))) @@ -949,7 +949,7 @@ module csr_regfile mcause_d = mcause_q; mcounteren_d = mcounteren_q; mscratch_d = mscratch_q; - mtval_d = mtval_q; + if (CVA6Cfg.TvalEn) mtval_d = mtval_q; if (CVA6Cfg.RVH) begin mtinst_d = mtinst_q; mtval2_d = mtval2_q; @@ -1720,9 +1720,10 @@ module csr_regfile default: update_access_exception = 1'b1; endcase end - - mstatus_d.sxl = riscv::XLEN_64; - mstatus_d.uxl = riscv::XLEN_64; + if (CVA6Cfg.IS_XLEN64) begin + mstatus_d.sxl = riscv::XLEN_64; + mstatus_d.uxl = riscv::XLEN_64; + end if (!CVA6Cfg.RVU) begin mstatus_d.mpp = riscv::PRIV_LVL_M; end @@ -2506,18 +2507,16 @@ module csr_regfile // sequential process always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin - priv_lvl_q <= riscv::PRIV_LVL_M; + priv_lvl_q <= riscv::PRIV_LVL_M; // floating-point registers - fcsr_q <= '0; + fcsr_q <= '0; // debug signals - debug_mode_q <= 1'b0; if (CVA6Cfg.DebugEn) begin - dcsr_q <= '0; - dcsr_q.prv <= riscv::PRIV_LVL_M; - dcsr_q.xdebugver <= 4'h4; - dpc_q <= '0; - dscratch0_q <= {CVA6Cfg.XLEN{1'b0}}; - dscratch1_q <= {CVA6Cfg.XLEN{1'b0}}; + debug_mode_q <= 1'b0; + dcsr_q <= '{xdebugver: 4'h4, prv: riscv::PRIV_LVL_M, default: '0}; + dpc_q <= '0; + dscratch0_q <= {CVA6Cfg.XLEN{1'b0}}; + dscratch1_q <= {CVA6Cfg.XLEN{1'b0}}; end // machine mode registers mstatus_q <= 64'b0; @@ -2530,12 +2529,12 @@ module csr_regfile mcause_q <= {CVA6Cfg.XLEN{1'b0}}; mcounteren_q <= {CVA6Cfg.XLEN{1'b0}}; mscratch_q <= {CVA6Cfg.XLEN{1'b0}}; - mtval_q <= {CVA6Cfg.XLEN{1'b0}}; - fiom_q <= '0; - dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; - icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; - mcountinhibit_q <= '0; - acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator}; + if (CVA6Cfg.TvalEn) mtval_q <= {CVA6Cfg.XLEN{1'b0}}; + fiom_q <= '0; + dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; + icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; + mcountinhibit_q <= '0; + acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator}; // supervisor mode registers if (CVA6Cfg.RVS) begin medeleg_q <= {CVA6Cfg.XLEN{1'b0}}; @@ -2734,7 +2733,7 @@ module csr_regfile assign rvfi_csr_o.mscratch_q = mscratch_q; assign rvfi_csr_o.mepc_q = mepc_q; assign rvfi_csr_o.mcause_q = mcause_q; - assign rvfi_csr_o.mtval_q = mtval_q; + assign rvfi_csr_o.mtval_q = CVA6Cfg.TvalEn ? mtval_q : '0; assign rvfi_csr_o.fiom_q = fiom_q; assign rvfi_csr_o.mcountinhibit_q = mcountinhibit_q; assign rvfi_csr_o.cycle_q = cycle_q; diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index d1d7e2116..d1faa01b3 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -77,13 +77,18 @@ module cva6_fifo_v3 #( read_pointer_n = read_pointer_q; write_pointer_n = write_pointer_q; status_cnt_n = status_cnt_q; - data_ft_n = data_ft_q; - first_word_n = first_word_q; + if (FPGA_EN && FPGA_ALTERA) data_ft_n = data_ft_q; + if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q; if (FPGA_EN) begin fifo_ram_we = '0; fifo_ram_write_address = '0; fifo_ram_wdata = '0; - data_o = (DEPTH == 0) ? data_i : (first_word_q ? data_ft_q : fifo_ram_rdata); + if (DEPTH == 0) begin + data_o = data_i; + end else begin + if (FPGA_ALTERA) data_o = first_word_q ? data_ft_q : fifo_ram_rdata; + else data_o = fifo_ram_rdata; + end end else begin data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q]; mem_n = mem_q; @@ -96,7 +101,7 @@ module cva6_fifo_v3 #( fifo_ram_we = 1'b1; fifo_ram_write_address = write_pointer_q; fifo_ram_wdata = data_i; - first_word_n = FPGA_ALTERA && first_word_q && pop_i; + if (FPGA_ALTERA) first_word_n = first_word_q && pop_i; end else begin // push the data onto the queue mem_n[write_pointer_q] = data_i; @@ -113,7 +118,7 @@ module cva6_fifo_v3 #( if (pop_i && ~empty_o) begin data_ft_n = data_i; - first_word_n = FPGA_EN && FPGA_ALTERA && first_word_q && push_i; + if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q && push_i; // read from the queue is a default assignment // but increment the read pointer... if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0; @@ -151,8 +156,8 @@ module cva6_fifo_v3 #( read_pointer_q <= '0; write_pointer_q <= '0; status_cnt_q <= '0; - first_word_q <= '0; - data_ft_q <= '0; + if (FPGA_ALTERA) first_word_q <= '0; + if (FPGA_ALTERA) data_ft_q <= '0; end else begin if (flush_i) begin read_pointer_q <= '0; diff --git a/core/cvxif_issue_register_commit_if_driver.sv b/core/cvxif_issue_register_commit_if_driver.sv index 16ebaa5bc..88efc0002 100644 --- a/core/cvxif_issue_register_commit_if_driver.sv +++ b/core/cvxif_issue_register_commit_if_driver.sv @@ -36,16 +36,14 @@ module cvxif_issue_register_commit_if_driver #( input logic [31:0] x_off_instr_i, input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i, input [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0][CVA6Cfg.XLEN-1:0] register_i, - input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i, - output logic cvxif_busy_o + input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i ); // X_ISSUE_REGISTER_SPLIT = 0 : Issue and register transactions are synchrone // Mandatory assignement assign register_valid_o = issue_valid_o; assign register_o.hartid = issue_req_o.hartid; assign register_o.id = issue_req_o.id; - // cvxif can not take any more instruction if issue transaction is still up. - assign cvxif_busy_o = issue_valid_o && ~issue_ready_i; + always_comb begin issue_valid_o = valid_i && ~flush_i; issue_req_o.instr = x_off_instr_i; diff --git a/core/decoder.sv b/core/decoder.sv index 169c9b628..40db72b5e 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -812,10 +812,11 @@ module decoder unique case ({ CVA6Cfg.RVB, CVA6Cfg.RVZiCond }) - 2'b00: illegal_instr = illegal_instr_non_bm; - 2'b01: illegal_instr = illegal_instr_non_bm & illegal_instr_zic; - 2'b10: illegal_instr = illegal_instr_non_bm & illegal_instr_bm; - 2'b11: illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic; + 2'b00: illegal_instr = illegal_instr_non_bm; + 2'b01: illegal_instr = illegal_instr_non_bm & illegal_instr_zic; + 2'b10: illegal_instr = illegal_instr_non_bm & illegal_instr_bm; + 2'b11: illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic; + default: ; // TODO: Check that default case is not synthesized. endcase end end diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 97360a3b8..1505140e8 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -240,7 +240,7 @@ module frontend 4'b0001: begin ras_pop = 1'b0; ras_push = 1'b0; - if (CVA6Cfg.BTBEntries && btb_prediction_shifted[i].valid) begin + if (CVA6Cfg.BTBEntries != 0 && btb_prediction_shifted[i].valid) begin predict_address = btb_prediction_shifted[i].target_address; cf_type[i] = ariane_pkg::JumpR; end diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 8ea332dc0..6d1b09df4 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -141,19 +141,22 @@ module issue_read_operands rs3_len_t operand_c_fpr; // output flipflop (ID <-> EX) fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_n, fu_data_q; - logic [ CVA6Cfg.XLEN-1:0] imm_forward_rs3; + logic [CVA6Cfg.VLEN-1:0] pc_n; + logic is_compressed_instr_n; + branchpredict_sbe_t branch_predict_n; + logic [CVA6Cfg.XLEN-1:0] imm_forward_rs3; - logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_q; - logic [ 1:0] fpu_fmt_q; - logic [ 2:0] fpu_rm_q; - logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_q; - logic [ 31:0] cvxif_off_instr_q; + logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_n, alu_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_n, mult_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_n, fpu_valid_q; + logic [1:0] fpu_fmt_n, fpu_fmt_q; + logic [2:0] fpu_rm_n, fpu_rm_q; + logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_n, alu2_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_n, lsu_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_n, csr_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_n, branch_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_n, cvxif_valid_q; + logic [31:0] cvxif_off_instr_n, cvxif_off_instr_q; logic cvxif_instruction_valid; //fwd logic @@ -197,7 +200,7 @@ module issue_read_operands // CVXIF Signals logic cvxif_req_allowed; - logic x_transaction_rejected; + logic x_transaction_rejected, x_transaction_rejected_n; logic [OPERANDS_PER_INSTR-1:0] rs_valid; logic [OPERANDS_PER_INSTR-1:0][CVA6Cfg.XLEN-1:0] rs; @@ -225,8 +228,7 @@ module issue_read_operands .x_off_instr_i (orig_instr_i[0]), .x_trans_id_i (issue_instr_i[0].trans_id), .register_i (rs), - .rs_valid_i (rs_valid), - .cvxif_busy_o () + .rs_valid_i (rs_valid) ); if (OPERANDS_PER_INSTR == 3) begin assign rs_valid = {~stall_rs3[0], ~stall_rs2[0], ~stall_rs1[0]}; @@ -284,7 +286,7 @@ module issue_read_operands // after a multiplication was issued we can only issue another multiplication // otherwise we will get contentions on the fixed latency bus - if (mult_valid_q) begin + if (|mult_valid_q) begin fus_busy[0].alu = 1'b1; fus_busy[0].ctrl_flow = 1'b1; fus_busy[0].csr = 1'b1; @@ -310,7 +312,7 @@ module issue_read_operands fus_busy[1].cvxif = 1'b1; unique case (issue_instr_i[0].fu) - NONE: fus_busy[1].none = 1'b1; + NONE: fus_busy[1].none = 1'b1; CTRL_FLOW: begin if (CVA6Cfg.SpeculativeSb) begin // Issue speculative instruction, will be removed on BMISS @@ -350,7 +352,7 @@ module issue_read_operands // Control hazard fus_busy[1] = '1; end - MULT: fus_busy[1].mult = 1'b1; + MULT: fus_busy[1].mult = 1'b1; FPU, FPU_VEC: begin fus_busy[1].fpu = 1'b1; fus_busy[1].fpu_vec = 1'b1; @@ -360,6 +362,7 @@ module issue_read_operands fus_busy[1].store = 1'b1; end CVXIF: ; + default: ; endcase end end @@ -776,6 +779,64 @@ module issue_read_operands end end + always_comb begin + alu_valid_n = '0; + lsu_valid_n = '0; + mult_valid_n = '0; + fpu_valid_n = '0; + fpu_fmt_n = '0; + fpu_rm_n = '0; + alu2_valid_n = '0; + csr_valid_n = '0; + branch_valid_n = '0; + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin + case (issue_instr_i[i].fu) + ALU: begin + if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin + alu2_valid_n[i] = 1'b1; + end else begin + alu_valid_n[i] = 1'b1; + end + end + CTRL_FLOW: begin + branch_valid_n[i] = 1'b1; + end + MULT: begin + mult_valid_n[i] = 1'b1; + end + LOAD, STORE: begin + lsu_valid_n[i] = 1'b1; + end + CSR: begin + csr_valid_n[i] = 1'b1; + end + default: begin + if (issue_instr_i[i].fu == FPU && CVA6Cfg.FpPresent) begin + fpu_valid_n[i] = 1'b1; + fpu_fmt_n = orig_instr.rftype.fmt; // fmt bits from instruction + fpu_rm_n = orig_instr.rftype.rm; // rm bits from instruction + end else if (issue_instr_i[i].fu == FPU_VEC && CVA6Cfg.FpPresent) begin + fpu_valid_n[i] = 1'b1; + fpu_fmt_n = orig_instr.rvftype.vfmt; // vfmt bits from instruction + fpu_rm_n = {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction + end + end + endcase + end + end + // if we got a flush request, de-assert the valid flag, otherwise we will start this + // functional unit with the wrong inputs + if (flush_i) begin + alu_valid_n = '0; + lsu_valid_n = '0; + mult_valid_n = '0; + fpu_valid_n = '0; + alu2_valid_n = '0; + csr_valid_n = '0; + branch_valid_n = '0; + end + end // FU select, assert the correct valid out signal (in the next cycle) // This needs to be like this to make verilator happy. I know its ugly. always_ff @(posedge clk_i or negedge rst_ni) begin @@ -790,91 +851,45 @@ module issue_read_operands csr_valid_q <= '0; branch_valid_q <= '0; end else begin - alu_valid_q <= '0; - lsu_valid_q <= '0; - mult_valid_q <= '0; - fpu_valid_q <= '0; - fpu_fmt_q <= '0; - fpu_rm_q <= '0; - alu2_valid_q <= '0; - csr_valid_q <= '0; - branch_valid_q <= '0; - // Exception pass through: - // If an exception has occurred simply pass it through - // we do not want to issue this instruction - for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin - case (issue_instr_i[i].fu) - ALU: begin - if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin - alu2_valid_q[i] <= 1'b1; - end else begin - alu_valid_q[i] <= 1'b1; - end - end - CTRL_FLOW: begin - branch_valid_q[i] <= 1'b1; - end - MULT: begin - mult_valid_q[i] <= 1'b1; - end - LOAD, STORE: begin - lsu_valid_q[i] <= 1'b1; - end - CSR: begin - csr_valid_q[i] <= 1'b1; - end - default: begin - if (issue_instr_i[i].fu == FPU && CVA6Cfg.FpPresent) begin - fpu_valid_q[i] <= 1'b1; - fpu_fmt_q <= orig_instr.rftype.fmt; // fmt bits from instruction - fpu_rm_q <= orig_instr.rftype.rm; // rm bits from instruction - end else if (issue_instr_i[i].fu == FPU_VEC && CVA6Cfg.FpPresent) begin - fpu_valid_q[i] <= 1'b1; - fpu_fmt_q <= orig_instr.rvftype.vfmt; // vfmt bits from instruction - fpu_rm_q <= {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction - end - end - endcase - end - end - // if we got a flush request, de-assert the valid flag, otherwise we will start this - // functional unit with the wrong inputs - if (flush_i) begin - alu_valid_q <= '0; - lsu_valid_q <= '0; - mult_valid_q <= '0; - fpu_valid_q <= '0; - alu2_valid_q <= '0; - csr_valid_q <= '0; - branch_valid_q <= '0; - end + alu_valid_q <= alu_valid_n; + lsu_valid_q <= lsu_valid_n; + mult_valid_q <= mult_valid_n; + fpu_valid_q <= fpu_valid_n; + fpu_fmt_q <= fpu_fmt_n; + fpu_rm_q <= fpu_rm_n; + alu2_valid_q <= alu2_valid_n; + csr_valid_q <= csr_valid_n; + branch_valid_q <= branch_valid_n; end end if (CVA6Cfg.CvxifEn) begin + always_comb begin + cvxif_valid_n = '0; + cvxif_off_instr_n = 32'b0; + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin + case (issue_instr_i[i].fu) + CVXIF: begin + cvxif_valid_n[i] = 1'b1; + cvxif_off_instr_n = orig_instr[i]; + end + default: ; + endcase + end + end + if (flush_i) begin + cvxif_valid_n = '0; + cvxif_off_instr_n = 32'b0; + end + end always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin cvxif_valid_q <= '0; cvxif_off_instr_q <= 32'b0; end else begin - cvxif_valid_q <= '0; - cvxif_off_instr_q <= 32'b0; - for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin - case (issue_instr_i[i].fu) - CVXIF: begin - cvxif_valid_q[i] <= 1'b1; - cvxif_off_instr_q <= orig_instr[i]; - end - default: ; - endcase - end - end - if (flush_i) begin - cvxif_valid_q <= '0; - cvxif_off_instr_q <= 32'b0; - end + cvxif_valid_q <= cvxif_valid_n; + cvxif_off_instr_q <= cvxif_off_instr_n; end end end @@ -1094,6 +1109,30 @@ module issue_read_operands // ---------------------- // Registers (ID <-> EX) // ---------------------- + + always_comb begin + pc_n = '0; + is_compressed_instr_n = 1'b0; + branch_predict_n = {cf_t'(0), {CVA6Cfg.VLEN{1'b0}}}; + if (CVA6Cfg.SuperscalarEn) begin + if (issue_instr_i[1].fu == CTRL_FLOW) begin + pc_n = issue_instr_i[1].pc; + is_compressed_instr_n = issue_instr_i[1].is_compressed; + branch_predict_n = issue_instr_i[1].bp; + end + end + if (issue_instr_i[0].fu == CTRL_FLOW) begin + pc_n = issue_instr_i[0].pc; + is_compressed_instr_n = issue_instr_i[0].is_compressed; + branch_predict_n = issue_instr_i[0].bp; + end + x_transaction_rejected_n = 1'b0; + if (issue_instr_i[0].fu == CVXIF) begin + x_transaction_rejected_n = x_transaction_rejected; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin fu_data_q <= '0; @@ -1109,22 +1148,10 @@ module issue_read_operands if (CVA6Cfg.RVH) begin tinst_q <= tinst_n; end - if (CVA6Cfg.SuperscalarEn) begin - if (issue_instr_i[1].fu == CTRL_FLOW) begin - pc_o <= issue_instr_i[1].pc; - is_compressed_instr_o <= issue_instr_i[1].is_compressed; - branch_predict_o <= issue_instr_i[1].bp; - end - end - if (issue_instr_i[0].fu == CTRL_FLOW) begin - pc_o <= issue_instr_i[0].pc; - is_compressed_instr_o <= issue_instr_i[0].is_compressed; - branch_predict_o <= issue_instr_i[0].bp; - end - x_transaction_rejected_o <= 1'b0; - if (issue_instr_i[0].fu == CVXIF) begin - x_transaction_rejected_o <= x_transaction_rejected; - end + pc_o <= pc_n; + is_compressed_instr_o <= is_compressed_instr_n; + branch_predict_o <= branch_predict_n; + x_transaction_rejected_o <= x_transaction_rejected_n; end end diff --git a/core/mult.sv b/core/mult.sv index 425965e40..ae4962ac8 100644 --- a/core/mult.sv +++ b/core/mult.sv @@ -67,8 +67,7 @@ module mult .result_o (mul_result), .mult_valid_i (mul_valid_op), .mult_valid_o (mul_valid), - .mult_trans_id_o(mul_trans_id), - .mult_ready_o () // this unit is unconditionally ready + .mult_trans_id_o(mul_trans_id) ); // --------------------- diff --git a/core/multiplier.sv b/core/multiplier.sv index 4a46ee671..b6c44f7f7 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -38,8 +38,6 @@ module multiplier output logic [ CVA6Cfg.XLEN-1:0] result_o, // Mutliplier result is valid - Mult output logic mult_valid_o, - // Multiplier FU is ready - Mult - output logic mult_ready_o, // Multiplier transaction ID - Mult output logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id_o ); @@ -90,7 +88,6 @@ module multiplier // control signals assign mult_valid_o = mult_valid_q; assign mult_trans_id_o = trans_id_q; - assign mult_ready_o = 1'b1; assign mult_valid = mult_valid_i && (operation_i inside {MUL, MULH, MULHU, MULHSU, MULW, CLMUL, CLMULH, CLMULR}); diff --git a/core/store_buffer.sv b/core/store_buffer.sv index 3c973e826..7c22a97fe 100644 --- a/core/store_buffer.sv +++ b/core/store_buffer.sv @@ -85,7 +85,6 @@ module store_buffer speculative_status_cnt = speculative_status_cnt_q; // default assignments - speculative_status_cnt_n = speculative_status_cnt_q; speculative_read_pointer_n = speculative_read_pointer_q; speculative_write_pointer_n = speculative_write_pointer_q; speculative_queue_n = speculative_queue_q; @@ -147,6 +146,7 @@ module store_buffer CVA6Cfg.DCACHE_INDEX_WIDTH-1 : CVA6Cfg.DCACHE_INDEX_WIDTH]; assign req_port_o.data_wdata = commit_queue_q[commit_read_pointer_q].data; + assign req_port_o.data_wuser = '0; assign req_port_o.data_be = commit_queue_q[commit_read_pointer_q].be; assign req_port_o.data_size = commit_queue_q[commit_read_pointer_q].data_size; diff --git a/spyglass/reference_summary.rpt b/spyglass/reference_summary.rpt index 8cd2eeaab..21af934a3 100644 --- a/spyglass/reference_summary.rpt +++ b/spyglass/reference_summary.rpt @@ -3,9 +3,9 @@ # # This file has been generated by SpyGlass: # Report Name : summary -# Report Created by: asintzoff -# Report Created on: Mon Sep 9 16:12:42 2024 -# Working Directory: /home/asintzoff/git-repo/tss/cva6/spyglass +# Report Created by: gchauvon +# Report Created on: Wed Jan 15 17:25:40 2025 +# Working Directory: /home/gchauvon/rhel8/github_issue/issue_2280/cva6/spyglass # SpyGlass Version : SpyGlass_vS-2021.09-SP2-3 # Policy Name : SpyGlass(SpyGlass_vS-2021.09-SP2-03) # erc(SpyGlass_vS-2021.09-SP2-03) @@ -17,9 +17,9 @@ # starc(SpyGlass_vS-2021.09-SP2-03) # starc2005(SpyGlass_vS-2021.09-SP2-03) # -# Total Number of Generated Messages : 1023 -# Number of Waived Messages : 327 -# Number of Reported Messages : 696 +# Total Number of Generated Messages : 977 +# Number of Waived Messages : 885 +# Number of Reported Messages : 92 # Number of Overlimit Messages : 0 # # @@ -54,17 +54,9 @@ INFO HdlLibDuCheck_03 1 Reports that 'hdllibdu' is not required +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Severity Rule Name Count Short Help =============================================================================== -WARNING SYNTH_12605 5 Used Priority/Unique Type case/if - statement but all the conditions are - not covered -WARNING SYNTH_12608 1 The logic of the always block - mismatches with the type of Always - Block -WARNING SYNTH_12611 2 Property blocks will be ignored for - synthesis -WARNING SYNTH_5064 38 Non-synthesizable statements are +WARNING SYNTH_5064 12 Non-synthesizable statements are ignored for synthesis. -WARNING SYNTH_5143 11 Initial block is ignored for synthesis +WARNING SYNTH_5143 1 Initial block is ignored for synthesis WARNING SYNTH_89 4 Initial Assignment at Declaration is ignored by synthesis. WARNING WRN_27 1 Bit-select should not be out-of-range. @@ -80,46 +72,21 @@ INFO ElabSummary 1 Generates Elaborated design units +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Severity Rule Name Count Short Help =============================================================================== -ERROR InferLatch 2 Latch inferred -ERROR UndrivenInTerm-ML 1 Undriven but loaded input terminal of - an instance detected -ERROR W123 11 A signal or variable has been read but +ERROR W123 12 A signal or variable has been read but is not set ERROR W416 1 Width of return type and return value of a function should be same (Verilog) Range of return type and return value of a function should be same (VHDL) -WARNING FlopEConst 19 Flip-flop enable pin is permanently - disabled or enabled -WARNING ParamWidthMismatch-ML 1 Parameter width does not match with the - value assigned -WARNING STARC05-1.3.1.3 1 Asynchronous reset/preset signals must - not be used as non-reset/preset or - synchronous reset/preset signals -WARNING STARC05-2.1.3.1 2 Bit-width of function arguments must - match bit-width of the corresponding - function inputs. -WARNING STARC05-2.1.4.5 1 Bit-wise operators must be used instead - of logic operators in multi-bit - operations. -WARNING STARC05-2.1.5.3 2 Conditional expressions should evaluate - to a scalar. -WARNING STARC05-2.2.3.3 14 Do not assign over the same signal in +WARNING STARC05-2.2.3.3 2 Do not assign over the same signal in an always construct for sequential circuits -WARNING W224 2 Multi-bit expression found when one-bit - expression expected WARNING W263 4 A case expression width does not match case select expression width -WARNING W287b 36 Output port of an instance is not +WARNING W287b 17 Output port of an instance is not connected -WARNING W415a 45 Signal may be multiply assigned (beside +WARNING W415a 33 Signal may be multiply assigned (beside initialization) in the same scope. -WARNING W480 3 Loop index is not of type integer -WARNING W486 2 Shift overflow - some bits may be lost -WARNING W528 482 A signal or variable is set but never - read -INFO W528 1 A signal or variable is set but never - read +WARNING W486 1 Shift overflow - some bits may be lost +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ diff --git a/spyglass/sg_setup/cva6/cva6_waiver.awl b/spyglass/sg_setup/cva6/cva6_waiver.awl index 44ca18666..7327998b3 100644 --- a/spyglass/sg_setup/cva6/cva6_waiver.awl +++ b/spyglass/sg_setup/cva6/cva6_waiver.awl @@ -6,9 +6,13 @@ ## Modified by : Asmaa Kassimi (asmaa.kassimi@external.thalesgroup.com) - Thales ####################################################################################################### -waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {55} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {85} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {SYNTH_5251} } +waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {55} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } +waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {85} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } +waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } +waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {SYNTH_5251} } waive -file { {$CVA6_REPO_DIR/common/local/util/tc_sram_wrapper_cache_techno.sv} } -du { {tc_sram_wrapper_cache_techno} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -rule { {W240} } -comment {Created by akassimi on 26-Jul-2024 18:36:59} + +waive -file {$CVA6_REPO_DIR/core/cache_subsystem/*} -regexp + +waive -rule { {W240} } -comment {Created by akassimi on 26-Jul-2024 18:36:59} +waive -rule { {W528} } -comment {Remove Set but not read warning as it happens very often for disable features such as PMP, Accelerator, ...} diff --git a/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch b/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch new file mode 100644 index 000000000..01410cbbd --- /dev/null +++ b/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch @@ -0,0 +1,16 @@ +diff --git a/vendor/pulp-platform/common_cells/src/popcount.sv b/vendor/pulp-platform/common_cells/src/popcount.sv +index 72b9b71f0..6fde114f3 100644 +--- a/vendor/pulp-platform/common_cells/src/popcount.sv ++++ b/vendor/pulp-platform/common_cells/src/popcount.sv +@@ -30,10 +30,7 @@ module popcount #( + logic [PopcountWidth-2:0] left_child_result, right_child_result; + + //Zero pad the input to next power of two +- always_comb begin +- padded_input = '0; +- padded_input[INPUT_WIDTH-1:0] = data_i; +- end ++ assign padded_input = {{{PaddedWidth-INPUT_WIDTH}{1'b0}}, data_i}; + + //Recursive instantiation to build binary adder tree + if (INPUT_WIDTH == 1) begin : single_node diff --git a/vendor/pulp-platform/common_cells/src/popcount.sv b/vendor/pulp-platform/common_cells/src/popcount.sv index 72b9b71f0..6fde114f3 100644 --- a/vendor/pulp-platform/common_cells/src/popcount.sv +++ b/vendor/pulp-platform/common_cells/src/popcount.sv @@ -30,10 +30,7 @@ module popcount #( logic [PopcountWidth-2:0] left_child_result, right_child_result; //Zero pad the input to next power of two - always_comb begin - padded_input = '0; - padded_input[INPUT_WIDTH-1:0] = data_i; - end + assign padded_input = {{{PaddedWidth-INPUT_WIDTH}{1'b0}}, data_i}; //Recursive instantiation to build binary adder tree if (INPUT_WIDTH == 1) begin : single_node