From 437734ccd029da35be8fc5b4d0b9a639a46ea50b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=B4me=20Allart?= <come.allart@thalesgroup.com>
Date: Thu, 24 Aug 2023 15:40:13 +0200
Subject: [PATCH] update verif/.gitignore

---
 verif/.gitignore | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/verif/.gitignore b/verif/.gitignore
index 045476b06..993df2a7b 100644
--- a/verif/.gitignore
+++ b/verif/.gitignore
@@ -35,25 +35,25 @@ waves.shm/
 *.log
 stdout.txt
 .vscode
-cva6/tests/riscv-compliance/
-cva6/tests/riscv-arch-test/
-cva6/tests/riscv-tests/
-cva6/tests/riscv-isa-sim/
-cva6/sim/dv/
-cva6/sim/vcs_results
-cva6/sim/verilator_work
-cva6/sim/out_*
-cva6/sim/Mem_init.txt
-cva6/sim/*.txt
-cva6/sim/trace*
-cva6/sim/simv*
-cva6/sim/ucli.key
-cva6/sim/.inter*
-cva6/sim/.vcs*
-cva6/sim/inter*
-cva6/sim/novas*
-cva6/sim/verdiLog
-cva6/sim/Verdi.ses*
+tests/riscv-compliance/
+tests/riscv-arch-test/
+tests/riscv-tests/
+tests/riscv-isa-sim/
+sim/dv/
+sim/vcs_results
+sim/verilator_work
+sim/out_*
+sim/Mem_init.txt
+sim/*.txt
+sim/trace*
+sim/simv*
+sim/ucli.key
+sim/.inter*
+sim/.vcs*
+sim/inter*
+sim/novas*
+sim/verdiLog
+sim/Verdi.ses*
 riviera_results/
 */vendor_lib/dpi_dasm_spike/
 */vendor_lib/verilab/svlib/