From 4ca7a3ae38aaadd150ecb352e08097f1ea91b83b Mon Sep 17 00:00:00 2001 From: Jean-Roch Coulon Date: Thu, 17 Oct 2024 22:49:46 +0200 Subject: [PATCH] Fix: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN --- core/frontend/instr_queue.sv | 2 +- core/include/riscv_pkg.sv | 1 - core/instr_realign.sv | 24 ++++++++++++------------ verif/tb/uvmt/cva6_tb_wrapper.sv | 2 +- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index 56558f366..938473e26 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -369,7 +369,7 @@ module instr_queue end fetch_entry_o[NID].instruction = instr_data_out[i].instr; fetch_entry_o[NID].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; - fetch_entry_o[NID].ex.tval = {{64 - riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; + fetch_entry_o[NID].ex.tval = {{64 - CVA6Cfg.VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; fetch_entry_o[NID].branch_predict.cf = instr_data_out[i].cf; // Cannot output two CF the same cycle. pop_instr[i] = fetch_entry_fire[NID]; diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv index 647ff4c7b..40499c637 100644 --- a/core/include/riscv_pkg.sv +++ b/core/include/riscv_pkg.sv @@ -23,7 +23,6 @@ package riscv; // FIXME stop using them from CoreV-Verif and HPDCache // Then remove them from this package localparam XLEN = cva6_config_pkg::CVA6ConfigXlen; - localparam VLEN = (XLEN == 32) ? 32 : 64; localparam PLEN = (XLEN == 32) ? 34 : 56; // -------------------- diff --git a/core/instr_realign.sv b/core/instr_realign.sv index 9191285b6..3aae6ff92 100644 --- a/core/instr_realign.sv +++ b/core/instr_realign.sv @@ -127,7 +127,7 @@ module instr_realign instr_o[2] = '0; addr_o[2] = '0; instr_o[3] = {16'b0, data_i[63:48]}; - addr_o[3] = {address_i[riscv::VLEN-1:3], 3'b110}; + addr_o[3] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; case (address_i[2:1]) 2'b00: begin @@ -153,11 +153,11 @@ module instr_realign addr_o[0] = unaligned_address_q; instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b010}; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; if (instr_is_compressed[1]) begin instr_o[2] = data_i[63:32]; - addr_o[2] = {address_i[riscv::VLEN-1:3], 3'b100}; + addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; valid_o[2] = valid_i; if (instr_is_compressed[2]) begin @@ -189,7 +189,7 @@ module instr_realign if (instr_is_compressed[0]) begin instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b010}; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; // 64 48 32 16 0 // | 3 | 2 | 1 | 0 | <- instruction slot @@ -200,7 +200,7 @@ module instr_realign // | * | C | C | C | C | -> aligned if (instr_is_compressed[1]) begin instr_o[2] = data_i[63:32]; - addr_o[2] = {address_i[riscv::VLEN-1:3], 3'b100}; + addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; valid_o[2] = valid_i; if (instr_is_compressed[2]) begin @@ -231,7 +231,7 @@ module instr_realign // | * | C | C | I | // | * | I | I | instr_o[1] = data_i[63:32]; - addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b100}; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; instr_o[2] = instr_o[3]; addr_o[2] = addr_o[3]; @@ -262,15 +262,15 @@ module instr_realign // 000 110 100 010 <- unaligned address instr_o[0] = data_i[31:0]; - addr_o[0] = {address_i[riscv::VLEN-1:3], 3'b010}; + addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; valid_o[0] = valid_i; instr_o[2] = data_i[63:32]; - addr_o[2] = {address_i[riscv::VLEN-1:3], 3'b110}; + addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; if (instr_is_compressed[0]) begin instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b100}; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; valid_o[1] = valid_i; if (instr_is_compressed[1]) begin @@ -304,11 +304,11 @@ module instr_realign // 1000 110 100 <- unaligned address instr_o[0] = data_i[31:0]; - addr_o[0] = {address_i[riscv::VLEN-1:3], 3'b100}; + addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; valid_o[0] = valid_i; instr_o[1] = data_i[47:16]; - addr_o[1] = {address_i[riscv::VLEN-1:3], 3'b110}; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; if (instr_is_compressed[0]) begin if (instr_is_compressed[1]) begin @@ -330,7 +330,7 @@ module instr_realign // 1000 110 <- unaligned address instr_o[0] = data_i[31:0]; - addr_o[0] = {address_i[riscv::VLEN-1:3], 3'b110}; + addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; if (instr_is_compressed[0]) begin valid_o[0] = valid_i; diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv index 9b010f51d..6a063ef84 100644 --- a/verif/tb/uvmt/cva6_tb_wrapper.sv +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -68,7 +68,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( ) ( input logic clk_i, input logic rst_ni, - input logic [riscv::VLEN-1:0] boot_addr_i, + input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, output logic [31:0] tb_exit_o, output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, output rvfi_csr_t rvfi_csr_o,