diff --git a/src/fetch_fifo.sv b/src/fetch_fifo.sv
index 615fa4dc0..7095a4494 100644
--- a/src/fetch_fifo.sv
+++ b/src/fetch_fifo.sv
@@ -55,7 +55,7 @@ module fetch_fifo
     logic [$clog2(DEPTH)-1:0]     write_pointer_n,  write_pointer_q;
     logic [$clog2(DEPTH)-1:0]     status_cnt_n,     status_cnt_q; // this integer will be truncated by the synthesis tool
 
-    assign in_ready_o = !(status_cnt_q == DEPTH-2);
+    assign in_ready_o = (status_cnt_q < DEPTH-2);
     assign full = (status_cnt_q == DEPTH);
     assign empty = (status_cnt_q == '0);
 
diff --git a/src/instr_realigner.sv b/src/instr_realigner.sv
index 874bf0de9..e1ed74c52 100755
--- a/src/instr_realigner.sv
+++ b/src/instr_realigner.sv
@@ -102,10 +102,10 @@ module instr_realigner (
                         end
                     end
                 end
-                    // this is a full 32 bit instruction like
-                    // _______________________
-                    // | instruction [31:0]  |
-                    // |______________________
+                // this is a full 32 bit instruction like
+                // _______________________
+                // | instruction [31:0]  |
+                // |______________________
 
                 // we have an outstanding unaligned instruction
                 else if (unaligned_q) begin
@@ -166,8 +166,7 @@ module instr_realigner (
                 end
                 // there can never be a whole 32 bit instruction on a half word access
             end
-        end
-
+        end else
         // ----------------------------
         // Next compressed instruction
         // ----------------------------