diff --git a/src/util/instruction_trace_item.svh b/src/util/instruction_trace_item.svh index 8011731b7..dd167c145 100755 --- a/src/util/instruction_trace_item.svh +++ b/src/util/instruction_trace_item.svh @@ -54,6 +54,37 @@ class instruction_trace_item; endcase endfunction + function string csrAddrToStr(logic [11:0] addr); + case (addr) + CSR_SSTATUS: return "sstatus"; + CSR_SIE: return "sie"; + CSR_STVEC: return "stvec"; + CSR_SSCRATCH: return "sscratch"; + CSR_SEPC: return "sepc"; + CSR_SCAUSE: return "scause"; + CSR_STVAL: return "stval"; + CSR_SIP: return "sip"; + CSR_SATP: return "satp"; + + CSR_MSTATUS: return "mstatus"; + CSR_MISA: return "misa"; + CSR_MEDELEG: return "medeleg"; + CSR_MIDELEG: return "mideleg"; + CSR_MIE: return "mie"; + CSR_MTVEC: return "mtvec"; + CSR_MSCRATCH: return "mscratch"; + CSR_MEPC: return "mepc"; + CSR_MCAUSE: return "mcause"; + CSR_MTVAL: return "mtval"; + CSR_MIP: return "mip"; + CSR_MVENDORID: return "mvendorid"; + CSR_MARCHID: return "marchid"; + CSR_MIMPID: return "mimpid"; + CSR_MHARTID: return "mhartid"; + default: return $sformatf("%0h", addr); + endcase + endfunction + function string printInstr(); string s; @@ -63,16 +94,22 @@ class instruction_trace_item; // Regular opcodes INSTR_LUI: s = this.printUInstr("lui"); INSTR_AUIPC: s = this.printUInstr("auipc"); + INSTR_J: s = this.printUJInstr("j"); INSTR_JAL: s = this.printUJInstr("jal"); INSTR_JALR: s = this.printIInstr("jalr"); // BRANCH + INSTR_BEQZ: s = this.printSBInstr("beqz"); INSTR_BEQ: s = this.printSBInstr("beq"); + INSTR_BNEZ: s = this.printSBInstr("bnez"); INSTR_BNE: s = this.printSBInstr("bne"); + INSTR_BLTZ: s = this.printSBInstr("bltz"); INSTR_BLT: s = this.printSBInstr("blt"); + INSTR_BGEZ: s = this.printSBInstr("bgez"); INSTR_BGE: s = this.printSBInstr("bge"); INSTR_BLTU: s = this.printSBInstr("bltu"); INSTR_BGEU: s = this.printSBInstr("bgeu"); // OPIMM + INSTR_LI: s = this.printIInstr("li"); INSTR_ADDI: s = this.printIInstr("addi"); INSTR_SLTI: s = this.printIInstr("slti"); INSTR_SLTIU: s = this.printIInstr("sltiu"); @@ -97,9 +134,14 @@ class instruction_trace_item; INSTR_FENCE: s = this.printMnemonic("fence"); INSTR_FENCEI: s = this.printMnemonic("fencei"); // SYSTEM (CSR manipulation) + INSTR_CSRW: s = this.printCSRInstr("csrw"); INSTR_CSRRW: s = this.printCSRInstr("csrrw"); + INSTR_CSRR: s = this.printCSRInstr("csrr"); INSTR_CSRRS: s = this.printCSRInstr("csrrs"); + INSTR_CSRS: s = this.printCSRInstr("csrs"); INSTR_CSRRC: s = this.printCSRInstr("csrrc"); + INSTR_CSRC: s = this.printCSRInstr("csrc"); + INSTR_CSRRWI: s = this.printCSRInstr("csrrwi"); INSTR_CSRRSI: s = this.printCSRInstr("csrrsi"); INSTR_CSRRCI: s = this.printCSRInstr("csrrci"); @@ -160,6 +202,9 @@ class instruction_trace_item; result_regs.push_back(sbe.rd); read_regs.push_back(sbe.rs1); + if (sbe.rs1 == 0) + return $sformatf("%-16s %s, %0d", mnemonic, regAddrToStr(sbe.rd), $signed(sbe.result)); + return $sformatf("%-16s %s, %s, %0d", mnemonic, regAddrToStr(sbe.rd), regAddrToStr(sbe.rs1), $signed(sbe.result)); endfunction // printIInstr @@ -168,40 +213,48 @@ class instruction_trace_item; result_regs.push_back(sbe.rd); read_regs.push_back(sbe.rs1); - return $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, sbe.rd, sbe.rs1, sbe.result); + return $sformatf("%-16s %s, %s, 0x%0x", mnemonic, regAddrToStr(sbe.rd), regAddrToStr(sbe.rs1), sbe.result); endfunction // printIuInstr function string printSBInstr(input string mnemonic); - result_regs.push_back(sbe.rd); - read_regs.push_back(sbe.rs1); + result_regs.push_back(sbe.rs1); + read_regs.push_back(sbe.rs2); - return $sformatf("%-16s %s, %s, 0x%0x", mnemonic, regAddrToStr(sbe.rd), regAddrToStr(sbe.rs1), sbe.result); + if (sbe.rs2 == 0) + return $sformatf("%-16s %s, pc + %0d", mnemonic, regAddrToStr(sbe.rs1), $signed(sbe.result)); + else + return $sformatf("%-16s %s, %s, pc + %0d", mnemonic, regAddrToStr(sbe.rs1), regAddrToStr(sbe.rs2), $signed(sbe.result)); endfunction // printIuInstr function string printUInstr(input string mnemonic); result_regs.push_back(sbe.rd); - return $sformatf("%-16s x%0d, 0x%0h", mnemonic, sbe.rd, sbe.result); + return $sformatf("%-16s %s, 0x%0h", mnemonic, regAddrToStr(sbe.rd), sbe.result[31:12]); endfunction // printUInstr function string printUJInstr(input string mnemonic); result_regs.push_back(sbe.rd); - - return $sformatf("%-16s x%0d, %0d", mnemonic, sbe.rd, $signed(sbe.result)); + // jump instruction + if (sbe.rd == 0) + return $sformatf("%-16s pc + %0d", mnemonic, $signed(sbe.result)); + else + return $sformatf("%-16s %s, pc + %0d", mnemonic, regAddrToStr(sbe.rd), $signed(sbe.result)); endfunction // printUJInstr function string printCSRInstr(input string mnemonic); result_regs.push_back(sbe.rd); read_regs.push_back(sbe.rs1); - - if (instr[14] == 1'b0) begin - return $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, sbe.rd, sbe.rs1, sbe.result[11:0]); - end else begin - return $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, sbe.rd, sbe.rs1, sbe.result[11:0]); + if (sbe.rd != 0 && sbe.rs1 != 0) begin + return $sformatf("%-16s %s, %s, %s", mnemonic, regAddrToStr(sbe.rd), regAddrToStr(sbe.rs1), csrAddrToStr(sbe.result[11:0])); + // don't display instructions which write to zero + end else if (sbe.rd == 0) begin + return $sformatf("%-16s %s, %s", mnemonic, regAddrToStr(sbe.rs1), csrAddrToStr(sbe.result[11:0])); + end else if (sbe.rs1 == 0) begin + return $sformatf("%-16s %s, %s", mnemonic, regAddrToStr(sbe.rd), csrAddrToStr(sbe.result[11:0])); end endfunction // printCSRInstr diff --git a/src/util/instruction_tracer_defines.svh b/src/util/instruction_tracer_defines.svh index 27d238efb..64ca1bea2 100755 --- a/src/util/instruction_tracer_defines.svh +++ b/src/util/instruction_tracer_defines.svh @@ -20,16 +20,22 @@ parameter INSTR_LUI = { 25'b?, OPCODE_LUI }; parameter INSTR_AUIPC = { 25'b?, OPCODE_AUIPC }; parameter INSTR_JAL = { 25'b?, OPCODE_JAL }; +parameter INSTR_J = { 20'b?, 5'b0, OPCODE_JAL }; parameter INSTR_JALR = { 17'b?, 3'b000, 5'b?, OPCODE_JALR }; // BRANCH -parameter INSTR_BEQ = { 17'b?, 3'b000, 5'b?, OPCODE_BRANCH }; -parameter INSTR_BNE = { 17'b?, 3'b001, 5'b?, OPCODE_BRANCH }; -parameter INSTR_BLT = { 17'b?, 3'b100, 5'b?, OPCODE_BRANCH }; -parameter INSTR_BGE = { 17'b?, 3'b101, 5'b?, OPCODE_BRANCH }; -parameter INSTR_BLTU = { 17'b?, 3'b110, 5'b?, OPCODE_BRANCH }; -parameter INSTR_BGEU = { 17'b?, 3'b111, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BEQZ = { 7'b?, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BEQ = { 7'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BNEZ = { 7'b?, 5'b0, 5'b?, 3'b001, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BNE = { 7'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BLTZ = { 7'b?, 5'b0, 5'b?, 3'b100, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BLT = { 7'b?, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BGEZ = { 7'b?, 5'b0, 5'b?, 3'b101, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BGE = { 7'b?, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BLTU = { 7'b?, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BGEU = { 7'b?, 5'b?, 5'b?, 3'b111, 5'b?, OPCODE_BRANCH }; // OPIMM +parameter INSTR_LI = { 12'b?, 5'b0, 3'b000, 5'b?, OPCODE_OPIMM }; parameter INSTR_ADDI = { 17'b?, 3'b000, 5'b?, OPCODE_OPIMM }; parameter INSTR_SLTI = { 17'b?, 3'b010, 5'b?, OPCODE_OPIMM }; parameter INSTR_SLTIU = { 17'b?, 3'b011, 5'b?, OPCODE_OPIMM }; @@ -54,12 +60,18 @@ parameter INSTR_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, OPCODE_OP }; parameter INSTR_FENCE = { 4'b0, 8'b?, 13'b0, OPCODE_FENCE }; parameter INSTR_FENCEI = { 17'b0, 3'b001, 5'b0, OPCODE_FENCE }; // SYSTEM -parameter INSTR_CSRRW = { 17'b?, 3'b001, 5'b?, OPCODE_SYSTEM }; -parameter INSTR_CSRRS = { 17'b?, 3'b010, 5'b?, OPCODE_SYSTEM }; -parameter INSTR_CSRRC = { 17'b?, 3'b011, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRW = { 12'b?, 5'b?, 3'b001, 5'b0, OPCODE_SYSTEM }; +parameter INSTR_CSRRW = { 12'b?, 5'b?, 3'b001, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRR = { 12'b?, 5'b0, 3'b010, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRRS = { 12'b?, 5'b?, 3'b010, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRS = { 12'b?, 5'b?, 3'b010, 5'b0, OPCODE_SYSTEM }; +parameter INSTR_CSRRC = { 12'b?, 5'b?, 3'b011, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRC = { 12'b?, 5'b?, 3'b011, 5'b0, OPCODE_SYSTEM }; + parameter INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, OPCODE_SYSTEM }; parameter INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, OPCODE_SYSTEM }; parameter INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, OPCODE_SYSTEM }; + parameter INSTR_ECALL = { 12'b000000000000, 13'b0, OPCODE_SYSTEM }; parameter INSTR_EBREAK = { 12'b000000000001, 13'b0, OPCODE_SYSTEM }; parameter INSTR_ERET = { 12'b000100000000, 13'b0, OPCODE_SYSTEM }; diff --git a/tb/agents/core_if/core_if_driver.svh b/tb/agents/core_if/core_if_driver.svh index b1d65516d..338526842 100644 --- a/tb/agents/core_if/core_if_driver.svh +++ b/tb/agents/core_if/core_if_driver.svh @@ -38,7 +38,7 @@ class core_if_driver extends uvm_driver #(core_if_seq_item); // seq_item_port.item_done(); m_vif.mck.test_en <= 1'b0; m_vif.mck.clock_en <= 1'b1; - m_vif.mck.boot_addr <= 64'h800000; + m_vif.mck.boot_addr <= 64'h80000000; m_vif.mck.core_id <= 4'b0; m_vif.mck.cluster_id <= 6'b0; m_vif.mck.irq <= 1'b0;