diff --git a/.gitmodules b/.gitmodules
index 1618c3f09..340e7fe1c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "uvm-scaffold"]
 	path = uvm-scaffold
 	url = git@iis-git.ee.ethz.ch:floce/uvm-scaffold.git
+[submodule "lib/riscv-fesvr"]
+	path = lib/riscv-fesvr
+	url = git@iis-git.ee.ethz.ch:floce/riscv-fesvr.git
diff --git a/lib/riscv-fesvr b/lib/riscv-fesvr
new file mode 160000
index 000000000..14f61ce48
--- /dev/null
+++ b/lib/riscv-fesvr
@@ -0,0 +1 @@
+Subproject commit 14f61ce4833126b1327926ad12f7d7bc653702b6
diff --git a/src/pcgen.sv b/src/pcgen.sv
index 6249b140c..ac483a21e 100644
--- a/src/pcgen.sv
+++ b/src/pcgen.sv
@@ -49,7 +49,7 @@ module pcgen (
     assign fetch_address_o = npc_q;
 
     btb #(
-        .NR_ENTRIES(64),
+        .NR_ENTRIES(4096),
         .BITS_SATURATION_COUNTER(2)
     )
     btb_i
diff --git a/src/util/instruction_trace_item.svh b/src/util/instruction_trace_item.svh
index 32a8ba4ae..d083e940e 100755
--- a/src/util/instruction_trace_item.svh
+++ b/src/util/instruction_trace_item.svh
@@ -153,8 +153,11 @@ class instruction_trace_item;
             INSTR_CSRRC:               s = this.printCSRInstr("csrrc");
             INSTR_CSRC:                s = this.printCSRInstr("csrc");
 
+            INSTR_CSRWI:               s = this.printCSRInstr("csrwi");
             INSTR_CSRRWI:              s = this.printCSRInstr("csrrwi");
+            INSTR_CSRSI:               s = this.printCSRInstr("csrsi");
             INSTR_CSRRSI:              s = this.printCSRInstr("csrrsi");
+            INSTR_CSRCI:               s = this.printCSRInstr("csrci");
             INSTR_CSRRCI:              s = this.printCSRInstr("csrrci");
             // SYSTEM (others)
             INSTR_ECALL:               s = this.printMnemonic("ecall");
diff --git a/src/util/instruction_tracer_defines.svh b/src/util/instruction_tracer_defines.svh
index 8a93eedee..00ba5cd02 100755
--- a/src/util/instruction_tracer_defines.svh
+++ b/src/util/instruction_tracer_defines.svh
@@ -83,8 +83,11 @@ parameter INSTR_CSRS     =  { 12'b?, 5'b?, 3'b010, 5'b0, OPCODE_SYSTEM };
 parameter INSTR_CSRRC    =  { 12'b?, 5'b?, 3'b011, 5'b?, OPCODE_SYSTEM };
 parameter INSTR_CSRC     =  { 12'b?, 5'b?, 3'b011, 5'b0, OPCODE_SYSTEM };
 
+parameter INSTR_CSRWI    =  { 17'b?, 3'b101, 5'b0, OPCODE_SYSTEM };
 parameter INSTR_CSRRWI   =  { 17'b?, 3'b101, 5'b?, OPCODE_SYSTEM };
+parameter INSTR_CSRSI    =  { 17'b?, 3'b110, 5'b0, OPCODE_SYSTEM };
 parameter INSTR_CSRRSI   =  { 17'b?, 3'b110, 5'b?, OPCODE_SYSTEM };
+parameter INSTR_CSRCI    =  { 17'b?, 3'b111, 5'b0, OPCODE_SYSTEM };
 parameter INSTR_CSRRCI   =  { 17'b?, 3'b111, 5'b?, OPCODE_SYSTEM };
 
 parameter INSTR_ECALL    =  { 12'b000000000000, 13'b0, OPCODE_SYSTEM };