diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 31702f82b..446039111 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -23,15 +23,16 @@ variables: stages: - build - - test + - test_std +# prepare build: stage: build script: - ci/build-riscv-tests.sh + - ci/get-torture.sh - make clean - - make build questa_version=$QUESTASIM_VERSION - - make verilate verilator=$VERILATOR_ROOT/bin/verilator + - make torture-gen artifacts: paths: - tmp @@ -74,4 +75,16 @@ run-benchmarks-verilator: dependencies: - build +torture-quest: + stage: test_std + script: + - make torture-rtest + dependencies: + - build +torture-ver: + stage: test_std + script: + - make torture-rtest-verilator + dependencies: + - build diff --git a/.travis.yml b/.travis.yml index 2b79f55a4..3bed9d176 100644 --- a/.travis.yml +++ b/.travis.yml @@ -29,6 +29,7 @@ addons: - texinfo - python-pexpect - libusb-1.0-0-dev + - default-jdk env: global: - RISCV="/home/travis/riscv_install" @@ -86,5 +87,12 @@ jobs: script: - ci/build-riscv-tests.sh - make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator + - stage: test + name: run torture + script: + - ci/get-torture.sh + - make clean + - make torture-gen + - make torture-rtest-verilator verilator=$VERILATOR_ROOT/bin/verilator # extra time during long builds install: travis_wait diff --git a/Makefile b/Makefile index 157e960b2..49c77b39a 100755 --- a/Makefile +++ b/Makefile @@ -17,14 +17,16 @@ questa_version ?= ${QUESTASIM_VERSION} verilator ?= verilator # traget option target-options ?= +# additional definess +defines ?= # Sources # Package files -> compile first -ariane_pkg := include/riscv_pkg.sv \ - src/debug/dm_pkg.sv \ - src/axi/src/axi_pkg.sv \ - include/ariane_pkg.sv \ - include/std_cache_pkg.sv \ - include/axi_if.sv +ariane_pkg := include/riscv_pkg.sv \ + src/debug/dm_pkg.sv \ + src/axi/src/axi_pkg.sv \ + include/ariane_pkg.sv \ + include/std_cache_pkg.sv \ + include/axi_if.sv # utility modules util := $(wildcard src/util/*.svh) \ @@ -63,11 +65,12 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ - +# root path +root-dir := $(shell pwd) # look for testbenches tbs := tb/ariane_tb.sv tb/ariane_testharness.sv # RISCV asm tests and benchmark setup (used for CI) -# there is a defined test-list with selected CI tests +# there is a definesd test-list with selected CI tests riscv-test-dir := tmp/riscv-tests/build/isa/ riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/ riscv-asm-tests-list := ci/riscv-asm-tests.list @@ -76,17 +79,20 @@ riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-) # preset which runs a single test riscv-test ?= rv64ui-p-add -# failed test directory -failed-tests := $(wildcard failedtests/*.S) + # Search here for include files (e.g.: non-standalone components) incdir := ./includes # Compile and sim flags -compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines) uvm-flags += +UVM_NO_RELNOTES # Iterate over all include directories and write them with +incdir+ prefixed # +incdir+ works for Verilator and QuestaSim list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir)) +# RISCV torture setup +riscv-torture-dir := tmp/riscv-torture/ +riscv-torture-bin := java -Xmx1G -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar + # Build the TB and module using QuestaSim build: $(library) $(library)/.build-srcs $(library)/.build-tb $(library)/ariane_dpi.so # Optimize top level @@ -107,10 +113,12 @@ $(library)/.build-tb: $(dpi) $(tbs) touch $(library)/.build-tb # compile DPIs -work/%.o: tb/dpi/%.cc $(dpi_hdr) +$(library)/%.o: tb/dpi/%.cc $(dpi_hdr) + mkdir -p $(library) $(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $< $(library)/ariane_dpi.so: $(dpi) + mkdir -p $(library) # Compile C-code and generate .so file $(CXX) -shared -m64 -o $(library)/ariane_dpi.so $? -lfesvr @@ -118,59 +126,57 @@ $(library): # Create the library vlib${questa_version} ${library} -# +jtag_rbb_enable=1 sim: build $(library)/ariane_dpi.so - vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \ + vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ + $(QUESTASIM_FLAGS) \ + -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \ ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options) simc: build $(library)/ariane_dpi.so vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " run -all; exit" \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ + $(QUESTASIM_FLAGS) \ + -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " run -all; exit" \ ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options) - $(riscv-asm-tests): build $(library)/ariane_dpi.so vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ + $(QUESTASIM_FLAGS) \ + -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \ -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log $(riscv-benchmarks): build $(library)/ariane_dpi.so vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ +BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \ + $(QUESTASIM_FLAGS) \ + -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \ -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ ${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log - # can use -jX to run ci tests in parallel using X processes run-asm-tests: $(riscv-asm-tests) make check-asm-tests check-asm-tests: - ci/check-tests.sh tmp/riscv-asm-tests- $(riscv-asm-tests-list) + ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }') # can use -jX to run ci tests in parallel using X processes run-benchmarks: $(riscv-benchmarks) make check-benchmarks check-benchmarks: - ci/check-tests.sh tmp/riscv-benchmarks- $(riscv-benchmarks-list) - + ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }') +# verilator-specific verilate_command := $(verilator) \ $(ariane_pkg) \ $(filter-out tb/ariane_bt.sv,$(src)) \ + +define+$(defines) \ src/util/sram.sv \ - +incdir+src/axi_node \ + +incdir+src/axi_node \ --unroll-count 256 \ -Werror-PINMISSING \ -Werror-IMPLICIT \ @@ -189,7 +195,7 @@ verilate_command := $(verilator) --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc # User Verilator, at some point in the future this will be auto-generated -verilate: +verilate: $(library)/ariane_dpi.so $(library)/SimJTAG.o $(library)/SimDTM.o $(library)/remote_bitbang.o $(verilate_command) cd build && make -j${NUM_JOBS} -f Variane_testharness.mk @@ -209,16 +215,54 @@ $(addsuffix -verilator,$(riscv-benchmarks)): verilate run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks)) - verify: qverify vlog -sv src/csr_regfile.sv -clean: - rm -rf work/ *.ucdb - rm -rf build - rm -f tmp/*.ucdb - rm -f tmp/*.log - rm -f *.wlf *vstf wlft* +# torture-specific +torture-gen: + cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run' +torture-itest: + cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S' + +torture-rtest: build + cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && make run-torture defines=$(defines)" > call.sh && chmod +x call.sh + cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log + make check-torture + +torture-rtest-verilator: verilate + cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && make run-torture-verilator defines=$(defines)" > call.sh && chmod +x call.sh + cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test-verilator.log + make check-torture-verilator + +run-torture: build $(library)/ariane_dpi.so + vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \ + +BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ + $(QUESTASIM_FLAGS) \ + -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \ + -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ + ${top_level}_optimized +permissive-off \ + +signature=$(riscv-torture-dir)/output/test.rtlsim.sig ++$(riscv-torture-dir)/output/test ++$(target-options) + +run-torture-verilator: verilate + build/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.verilator.sig $(riscv-torture-dir)/output/test + + +check-torture: + grep 'All signatures match for output/test' $(riscv-torture-dir)/output/test.log + diff -s $(riscv-torture-dir)/output/test.spike.sig $(riscv-torture-dir)/output/test.rtlsim.sig + +check-torture-verilator: + grep 'All signatures match for output/test' $(riscv-torture-dir)/output/test-verilator.log + diff -s $(riscv-torture-dir)/output/test.spike.sig $(riscv-torture-dir)/output/test.rtlsim.verilator.sig + +clean: + rm -rf $(riscv-torture-dir)/output/test* + rm -rf work/ *.ucdb build + rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* + .PHONY: - build lint build-moore $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) check simc sim verilate clean verilate + build lint build-moore check simc sim verilate clean verilate \ + $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \ + $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \ + torture-gen torture-igentest torture-rgentest torture-itest torture-rtest diff --git a/ci/default.config b/ci/default.config new file mode 100644 index 000000000..71a0b3766 --- /dev/null +++ b/ci/default.config @@ -0,0 +1,52 @@ +torture.generator.nseqs 1000 +torture.generator.memsize 1024 +torture.generator.fprnd 0 +torture.generator.amo false +torture.generator.mul true +torture.generator.divider true +torture.generator.segment true +torture.generator.loop true +torture.generator.loop_size 64 + +torture.generator.mix.xmem 15 +torture.generator.mix.xbranch 25 +torture.generator.mix.xalu 60 +torture.generator.mix.fgen 0 +torture.generator.mix.fpmem 0 +torture.generator.mix.fax 0 +torture.generator.mix.fdiv 0 +torture.generator.mix.vec 0 + +torture.generator.vec.vf 1 +torture.generator.vec.seq 20 +torture.generator.vec.memsize 128 +torture.generator.vec.numsregs 64 +torture.generator.vec.mul false +torture.generator.vec.div false +torture.generator.vec.mix true +torture.generator.vec.fpu false +torture.generator.vec.fma false +torture.generator.vec.fcvt false +torture.generator.vec.fdiv false +torture.generator.vec.amo false +torture.generator.vec.seg false +torture.generator.vec.stride false +torture.generator.vec.pred_alu true +torture.generator.vec.pred_mem true + +torture.generator.vec.mix.valu 20 +torture.generator.vec.mix.vpop 60 +torture.generator.vec.mix.vmem 20 +torture.generator.vec.mix.vonly 0 + +torture.testrun.maxcycles 10000000 +torture.testrun.virtual false +torture.testrun.seek true +torture.testrun.dump false +torture.testrun.vec false + +torture.overnight.errors 1 +torture.overnight.minutes 1 +torture.overnight.outdir output/failedtests +torture.overnight.email your@email.address + diff --git a/ci/get-torture.sh b/ci/get-torture.sh new file mode 100755 index 000000000..22ec2100c --- /dev/null +++ b/ci/get-torture.sh @@ -0,0 +1,21 @@ +#!/bin/bash +set -e +ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) +VERSION="59b0f0f224ff4f1eb6ebb1b4dd7eaf1ab3fac2e5" + +cd $ROOT/tmp + +if [ -z ${NUM_JOBS} ]; then + NUM_JOBS=1 +fi + +[ -d $ROOT/tmp/riscv-torture ] || git clone https://github.com/ucb-bar/riscv-torture.git +cd riscv-torture +git checkout $VERSION +git submodule update --init --recursive + +# copy ariane specific config +cp config/default.config config/default.config.bak +cp $ROOT/ci/default.config config/default.config +git apply $ROOT/ci/torture_make.patch + diff --git a/ci/torture_make.patch b/ci/torture_make.patch new file mode 100644 index 000000000..35114604c --- /dev/null +++ b/ci/torture_make.patch @@ -0,0 +1,41 @@ +diff --git a/output/Makefile b/output/Makefile +index cf1214f..c81bccc 100644 +--- a/output/Makefile ++++ b/output/Makefile +@@ -20,9 +20,9 @@ extra_files = + #-------------------------------------------------------------------- + + RISCV_GCC = riscv64-unknown-elf-gcc +-RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha ++RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=rv64imc + RISCV_OBJDUMP = riscv64-unknown-elf-objdump --disassemble-all --section=.text --section=.data --section=.bss +-RISCV_SIM = spike --extension=hwacha ++RISCV_SIM = spike + + #------------------------------------------------------------ + # Build assembly tests +@@ -38,9 +38,6 @@ $(asm_tests_dump): %.dump: % + $(asm_tests_bin): %: %.S $(extra_files) + $(RISCV_GCC) $(RISCV_GCC_OPTS) -I../env/p -T../env/p/link.ld $< -o $@ + +-$(asm_tests_hex): %.hex: % $(extra_files) +- elf2hex 16 16384 $< > $@ +- + $(asm_tests_sig): %.sig: % + $(RISCV_SIM) +signature=$@ $< + +@@ -51,12 +48,12 @@ run: $(asm_tests_sig) + echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \ + $(asm_tests_sig); echo; + +-junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) $(asm_tests_hex) ++junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) + + #------------------------------------------------------------ + # Default + +-all: $(asm_tests_dump) $(asm_tests_hex) ++all: $(asm_tests_dump) + + #------------------------------------------------------------ + # Clean up diff --git a/ci/travis-ci-emul.sh b/ci/travis-ci-emul.sh index d1267b7b5..1f46e75a1 100644 --- a/ci/travis-ci-emul.sh +++ b/ci/travis-ci-emul.sh @@ -38,3 +38,4 @@ make clean make -j${NUM_JOBS} verilate verilator=$VERILATOR_ROOT/bin/verilator make -j${NUM_JOBS} run-asm-tests-verilator verilator=$VERILATOR_ROOT/bin/verilator make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator +make -j${NUM_JOBS} run-torture-verilator verilator=$VERILATOR_ROOT/bin/verilator