diff --git a/src/lsu.sv b/src/lsu.sv
index 76f352dfa..17ce3f3ac 100644
--- a/src/lsu.sv
+++ b/src/lsu.sv
@@ -157,9 +157,9 @@ module lsu #(
         .ASID_WIDTH             ( ASID_WIDTH           )
     ) mmu_i (
         .lsu_req_i              ( translation_req      ),
-        .lsu_vaddr_i            ( vaddr                ),
-        .lsu_valid_o            ( translation_valid_n  ),
-        .lsu_paddr_o            ( paddr_n              ),
+        .lsu_vaddr_i            (                      ),
+        .lsu_valid_o            ( translation_valid    ),
+        .lsu_paddr_o            ( paddr                ),
         // connecting PTW to D$ IF (aka mem arbiter
         .data_if_address_o      ( address_i        [0] ),
         .data_if_data_wdata_o   ( data_wdata_i     [0] ),
@@ -172,10 +172,50 @@ module lsu #(
         .data_if_data_rdata_i   ( data_rdata_o     [0] ),
         .*
     );
+    logic st_valid_i;
+    logic st_ready_o;
+
+    logic                     ld_valid;
+    logic [TRANS_ID_BITS-1:0] ld_trans_id;
+    logic [63:0]              ld_result;
+    logic                     st_valid;
+    logic [TRANS_ID_BITS-1:0] st_trans_id;
+    logic [63:0]              st_result;
     // ------------------
     // Store Unit
     // ------------------
 
+    store_unit store_unit_i (
+        .operator_i            ( operator             ),
+        .trans_id_i            ( trans_id             ),
+        .valid_i               ( st_valid_i           ),
+        .vaddr_i               ( vaddr                ),
+        .be_i                  ( be                   ),
+        .data_i                ( data                 ),
+        .valid_o               ( st_valid             ),
+        .ready_o               ( st_ready_o           ),
+        .trans_id_o            ( st_trans_id          ),
+        .result_o              ( st_result            ),
+        // MMU port
+        .translation_req_o     (                      ),
+        .vaddr_o               (                      ),
+        .paddr_i               (                      ),
+        .translation_valid_i   (                      ),
+        // Load Unit
+        .page_offset_i         (                      ),
+        .page_offset_matches_o (                      ),
+        // Mem Arbiter
+        .address_o             ( address_i        [2] ),
+        .data_wdata_o          ( data_wdata_i     [2] ),
+        .data_req_o            ( data_req_i       [2] ),
+        .data_we_o             ( data_we_i        [2] ),
+        .data_be_o             ( data_be_i        [2] ),
+        .data_tag_status_o     ( data_tag_status_i[2] ),
+        .data_gnt_i            ( data_gnt_o       [2] ),
+        .data_rvalid_i         ( data_rvalid_o    [2] ),
+        .*
+    );
+
     // ------------------
     // Load Unit
     // ------------------
@@ -183,13 +223,6 @@ module lsu #(
     // ---------------------
     // Result Sequentialize
     // ---------------------
-
-    logic ld_valid_i;
-    logic [TRANS_ID_BITS-1:0] ld_trans_id;
-    logic [63:0] ld_result;
-    logic st_valid;
-    logic [TRANS_ID_BITS-1:0] st_trans_id;
-    logic [63:0] st_result;
     lsu_arbiter lsu_arbiter_i (
         .clk_i         ( clk_i          ),
         .rst_ni        ( rst_ni         ),
diff --git a/src/store_unit.sv b/src/store_unit.sv
index 37aebf3e1..0c8cb70ca 100644
--- a/src/store_unit.sv
+++ b/src/store_unit.sv
@@ -21,11 +21,14 @@ import ariane_pkg::*;
 module store_unit (
     input logic                      clk_i,    // Clock
     input logic                      rst_ni,  // Asynchronous reset active low
+    input logic                      flush_i,
     // store unit input port
-    input logic [1:0]                operator_i,
-    input logic                      valid_i,
-    input logic [63:0]               vaddr_i,
-    input logic [7:0]                be_i,
+    input  fu_op                     operator_i,
+    input  logic [TRANS_ID_BITS-1:0] trans_id_i,
+    input  logic                     valid_i,
+    input  logic [63:0]              vaddr_i,
+    input  logic [7:0]               be_i,
+    input  logic [63:0]              data_i,
     input  logic                     commit_i,
     // store unit output port
     output logic                     valid_o,
@@ -59,15 +62,42 @@ module store_unit (
     // store buffer control signals
     logic                    st_ready;
     logic                    st_valid;
+
+    assign vaddr_o = vaddr_i;
+    // ---------------
+    // Store Control
+    // ---------------
+    always_comb begin : store_control
+        translation_req_o = 1'b0;
+        valid_o           = 1'b0;
+        ready_o           = 1'b1;
+        trans_id_o        = trans_id_i;
+        st_valid          = 1'b0;
+        // we got a valid store
+        if (valid_i) begin
+            // first do address translation, we need to do it in the first cycle since we want to share the MMU
+            // between the load and the store unit. But we only know that when a new request arrives that we are not using
+            // it at the same time.
+            translation_req_o = 1'b1;
+            // check if translation was valid and we have space in the store buffer
+            // otherwise simply stall
+            if (translation_valid_i && st_ready) begin
+                valid_o  = 1'b0;
+                // post this store to the store buffer
+                st_valid = 1'b1;
+            // translation was not successful - stall here
+            end else begin
+                ready_o = 1'b0;
+            end
+        end
+    end
+
     // ---------------
     // Store Queue
     // ---------------
     store_queue store_queue_i (
         // store queue write port
         .valid_i           ( st_valid            ),
-        .paddr_i           ( paddr_q             ),
-        .data_i            ( data                ),
-        .be_i              ( be                  ),
         // store buffer in
         .paddr_o           ( st_buffer_paddr     ),
         .data_o            ( st_buffer_data      ),