diff --git a/ci/setup.sh b/ci/setup.sh index 325a15b6f..7e54b9775 100755 --- a/ci/setup.sh +++ b/ci/setup.sh @@ -11,7 +11,7 @@ export CPLUS_INCLUDE_PATH=$RISCV/include echo 'deb http://download.opensuse.org/repositories/home:/phiwag:/edatools/xUbuntu_20.04/ /' | sudo tee /etc/apt/sources.list.d/home:phiwag:edatools.list curl -fsSL https://download.opensuse.org/repositories/home:phiwag:edatools/xUbuntu_20.04/Release.key | gpg --dearmor | sudo tee /etc/apt/trusted.gpg.d/home_phiwag_edatools.gpg > /dev/null sudo apt update -sudo apt install verilator-4.100 device-tree-compiler +sudo apt install verilator-4.110 device-tree-compiler ci/make-tmp.sh sudo mkdir -p $RISCV && sudo chmod 777 $RISCV diff --git a/common/local/util/sram.sv b/common/local/util/sram.sv index 64c2b1d8c..1dd1a1f4c 100644 --- a/common/local/util/sram.sv +++ b/common/local/util/sram.sv @@ -20,6 +20,8 @@ module sram #( parameter DATA_WIDTH = 64, + parameter USER_WIDTH = 1, + parameter USER_EN = 0, parameter NUM_WORDS = 1024, parameter OUT_REGS = 0, // enables output registers in FPGA macro (read lat = 2) parameter DROMAJO_RAM = 0 @@ -29,26 +31,34 @@ module sram #( input logic req_i, input logic we_i, input logic [$clog2(NUM_WORDS)-1:0] addr_i, + input logic [USER_WIDTH-1:0] wuser_i, input logic [DATA_WIDTH-1:0] wdata_i, input logic [(DATA_WIDTH+7)/8-1:0] be_i, + output logic [USER_WIDTH-1:0] ruser_o, output logic [DATA_WIDTH-1:0] rdata_o ); localparam DATA_WIDTH_ALIGNED = ((DATA_WIDTH+63)/64)*64; +localparam USER_WIDTH_ALIGNED = DATA_WIDTH_ALIGNED; // To be fine tuned to reduce memory size localparam BE_WIDTH_ALIGNED = (((DATA_WIDTH+7)/8+7)/8)*8; logic [DATA_WIDTH_ALIGNED-1:0] wdata_aligned; +logic [USER_WIDTH_ALIGNED-1:0] wuser_aligned; logic [BE_WIDTH_ALIGNED-1:0] be_aligned; logic [DATA_WIDTH_ALIGNED-1:0] rdata_aligned; +logic [USER_WIDTH_ALIGNED-1:0] ruser_aligned; // align to 64 bits for inferrable macro below always_comb begin : p_align wdata_aligned ='0; + wuser_aligned ='0; be_aligned ='0; wdata_aligned[DATA_WIDTH-1:0] = wdata_i; + wuser_aligned[USER_WIDTH-1:0] = wuser_i; be_aligned[BE_WIDTH_ALIGNED-1:0] = be_i; rdata_o = rdata_aligned[DATA_WIDTH-1:0]; + ruser_o = ruser_aligned[USER_WIDTH-1:0]; end for (genvar k = 0; k<(DATA_WIDTH+63)/64; k++) begin : gen_cut @@ -67,6 +77,22 @@ end .Addr_DI ( addr_i ), .RdData_DO ( rdata_aligned[k*64 +: 64] ) ); + if (USER_EN) begin : gen_dromajo_user + dromajo_ram #( + .ADDR_WIDTH($clog2(NUM_WORDS)), + .DATA_DEPTH(NUM_WORDS), + .OUT_REGS (0) + ) i_ram_user ( + .Clk_CI ( clk_i ), + .Rst_RBI ( rst_ni ), + .CSel_SI ( req_i ), + .WrEn_SI ( we_i ), + .BEn_SI ( be_aligned[k*8 +: 8] ), + .WrData_DI ( wuser_aligned[k*64 +: 64] ), + .Addr_DI ( addr_i ), + .RdData_DO ( ruser_aligned[k*64 +: 64] ) + ); + end end else begin : gen_mem // unused byte-enable segments (8bits) are culled by the tool SyncSpRamBeNx64 #( @@ -86,6 +112,25 @@ end .Addr_DI ( addr_i ), .RdData_DO ( rdata_aligned[k*64 +: 64] ) ); + if (USER_EN) begin : gen_mem_user + SyncSpRamBeNx64 #( + .ADDR_WIDTH($clog2(NUM_WORDS)), + .DATA_DEPTH(NUM_WORDS), + .OUT_REGS (0), + // this initializes the memory with 0es. adjust to taste... + // 0: no init, 1: zero init, 2: random init, 3: deadbeef init + .SIM_INIT (1) + ) i_ram_user ( + .Clk_CI ( clk_i ), + .Rst_RBI ( rst_ni ), + .CSel_SI ( req_i ), + .WrEn_SI ( we_i ), + .BEn_SI ( be_aligned[k*8 +: 8] ), + .WrData_DI ( wuser_aligned[k*64 +: 64] ), + .Addr_DI ( addr_i ), + .RdData_DO ( ruser_aligned[k*64 +: 64] ) + ); + end end end endmodule : sram diff --git a/core/axi_shim.sv b/core/axi_shim.sv index 5b38aa71e..5a6c4c466 100644 --- a/core/axi_shim.sv +++ b/core/axi_shim.sv @@ -20,6 +20,7 @@ module axi_shim #( + parameter int unsigned AxiUserWidth = 64, // data width in dwords, this is also the maximum burst length, must be >=2 parameter int unsigned AxiNumWords = 4, // data width in dwords, this is also the maximum burst length, must be >=2 parameter int unsigned AxiIdWidth = 4 // stick to the spec ) ( @@ -39,6 +40,7 @@ module axi_shim #( output logic rd_last_o, output logic rd_valid_o, output logic [63:0] rd_data_o, + output logic [AxiUserWidth-1:0] rd_user_o, output logic [AxiIdWidth-1:0] rd_id_o, output logic rd_exokay_o, // indicates whether exclusive tx succeeded // write channel @@ -46,6 +48,7 @@ module axi_shim #( output logic wr_gnt_o, input logic [63:0] wr_addr_i, input logic [AxiNumWords-1:0][63:0] wr_data_i, + input logic [AxiNumWords-1:0][AxiUserWidth-1:0] wr_user_i, input logic [AxiNumWords-1:0][7:0] wr_be_i, input logic [$clog2(AxiNumWords)-1:0] wr_blen_i, // axi convention: LEN-1 input logic [1:0] wr_size_i, @@ -91,6 +94,7 @@ module axi_shim #( assign axi_req_o.aw.atop = wr_atop_i; // data assign axi_req_o.w.data = wr_data_i[wr_cnt_q]; + assign axi_req_o.w.user = wr_user_i[wr_cnt_q]; assign axi_req_o.w.strb = wr_be_i[wr_cnt_q]; assign axi_req_o.w.last = wr_cnt_done; @@ -252,6 +256,7 @@ module axi_shim #( // return path assign axi_req_o.r_ready = rd_rdy_i; assign rd_data_o = axi_resp_i.r.data; + assign rd_user_o = axi_resp_i.r.user; assign rd_last_o = axi_resp_i.r.last; assign rd_valid_o = axi_resp_i.r_valid; assign rd_id_o = axi_resp_i.r.id; diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index 6f388637b..690421998 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -81,7 +81,9 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #( logic [ICACHE_TAG_WIDTH-1:0] cl_tag_d, cl_tag_q; // this is the cache tag logic [ICACHE_TAG_WIDTH-1:0] cl_tag_rdata [ICACHE_SET_ASSOC-1:0]; // these are the tags coming from the tagmem logic [ICACHE_LINE_WIDTH-1:0] cl_rdata [ICACHE_SET_ASSOC-1:0]; // these are the cachelines coming from the cache + logic [ICACHE_USER_LINE_WIDTH-1:0] cl_ruser[ICACHE_SET_ASSOC-1:0]; // these are the cachelines coming from the user cache logic [ICACHE_SET_ASSOC-1:0][FETCH_WIDTH-1:0]cl_sel; // selected word from each cacheline + logic [ICACHE_SET_ASSOC-1:0][FETCH_USER_WIDTH-1:0] cl_user; // selected word from each cacheline logic [ICACHE_SET_ASSOC-1:0] vld_req; // bit enable for valid regs logic vld_we; // valid bits write enable logic [ICACHE_SET_ASSOC-1:0] vld_wdata; // valid bits to write @@ -389,6 +391,7 @@ end else begin : gen_piton_offset for (genvar i=0;i0 assign rdata_cl[i] = bank_rdata[bank_off_q[DCACHE_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES]][i]; + assign ruser_cl[i] = bank_ruser[bank_off_q[DCACHE_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES]][i]; end for(genvar k=0; k TX0: 0000_0001, TX1: 0000_1000, TX2: 0011_0000 - + assign miss_size_o = riscv::IS_XLEN64 ? toSize64(bdirty[dirty_ptr]): toSize32(bdirty[dirty_ptr]); // replicate transfers shorter than a dword assign miss_wdata_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]): repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]); + assign miss_wuser_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]): + repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]); assign tx_be = riscv::IS_XLEN64 ? to_byte_enable8(bdirty_off, miss_size_o[1:0]): to_byte_enable4(bdirty_off, miss_size_o[1:0]); @@ -291,6 +295,7 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #( assign wr_idx_o = wr_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; assign wr_off_o = wr_paddr[DCACHE_OFFSET_WIDTH-1:0]; assign wr_data_o = wbuffer_q[rtrn_ptr].data; + assign wr_user_o = wbuffer_q[rtrn_ptr].user; /////////////////////////////////////////////////////// @@ -391,10 +396,11 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #( assign req_port_o.data_rvalid = '0; assign req_port_o.data_rdata = '0; + assign req_port_o.data_ruser = '0; assign rd_hit_oh_d = rd_hit_oh_i; - - logic ni_inside,ni_conflict; + + logic ni_inside,ni_conflict; assign ni_inside = |ni_pending_q; assign ni_conflict = is_ni && ni_inside; assign not_ni_o = !ni_inside; @@ -471,11 +477,14 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #( wbuffer_d[wr_ptr].wtag = {req_port_i.address_tag, req_port_i.address_index[DCACHE_INDEX_WIDTH-1:riscv::XLEN_ALIGN_BYTES]}; // mark bytes as dirty + wbuffer_d[wr_ptr].user = '0; for (int k=0; k<(riscv::XLEN/8); k++) begin if (req_port_i.data_be[k]) begin wbuffer_d[wr_ptr].valid[k] = 1'b1; wbuffer_d[wr_ptr].dirty[k] = 1'b1; wbuffer_d[wr_ptr].data[k*8 +: 8] = req_port_i.data_wdata[k*8 +: 8]; + if (ariane_pkg::DATA_USER_EN) + wbuffer_d[wr_ptr].user[k*8 +: 8] = req_port_i.data_wuser[k*8 +: 8]; end end end @@ -552,7 +561,7 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #( else $fatal(1,"[l1 dcache wbuffer] req_port_i.kill_req should not be asserted"); for (genvar k=0; k FETCH_USER_WIDTH ? DATA_USER_WIDTH : FETCH_USER_WIDTH; + localparam DATA_USER_EN = cva6_config_pkg::CVA6ConfigDataUserEn; + localparam FETCH_USER_EN = cva6_config_pkg::CVA6ConfigFetchUserEn; + localparam AXI_USER_EN = cva6_config_pkg::CVA6ConfigDataUserEn | cva6_config_pkg::CVA6ConfigFetchUserEn; + + // --------------- // Fetch Stage // --------------- @@ -425,17 +437,20 @@ package ariane_pkg; localparam int unsigned DCACHE_TAG_WIDTH = riscv::PLEN - DCACHE_INDEX_WIDTH; `else // I$ - localparam int unsigned CONFIG_L1I_SIZE = 16*1024; + localparam int unsigned CONFIG_L1I_SIZE = 16*1024; localparam int unsigned ICACHE_SET_ASSOC = 4; // Must be between 4 to 64 localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); // in bit, contains also offset width localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN-ICACHE_INDEX_WIDTH; // in bit localparam int unsigned ICACHE_LINE_WIDTH = 128; // in bit + localparam int unsigned ICACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128; // in bit // D$ - localparam int unsigned CONFIG_L1D_SIZE = 32*1024; - localparam int unsigned DCACHE_SET_ASSOC = 8; // Must be between 4 to 64 + localparam int unsigned CONFIG_L1D_SIZE = 32*1024; + localparam int unsigned DCACHE_SET_ASSOC = 8; // Must be between 4 to 64 localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(CONFIG_L1D_SIZE / DCACHE_SET_ASSOC); // in bit, contains also offset width localparam int unsigned DCACHE_TAG_WIDTH = riscv::PLEN-DCACHE_INDEX_WIDTH; // in bit localparam int unsigned DCACHE_LINE_WIDTH = 128; // in bit + localparam int unsigned DCACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128; // in bit + localparam int unsigned DCACHE_USER_WIDTH = DATA_USER_WIDTH; `endif localparam bit CVXIF_PRESENT = cva6_config_pkg::CVA6ConfigCvxifEn; @@ -572,7 +587,7 @@ package ariane_pkg; default: return 1'b0; endcase endfunction - + typedef struct packed { logic valid; logic [riscv::VLEN-1:0] vaddr; @@ -701,6 +716,7 @@ package ariane_pkg; logic ready; // icache is ready logic valid; // signals a valid read logic [FETCH_WIDTH-1:0] data; // 2+ cycle out: tag + logic [FETCH_USER_WIDTH-1:0] user; // User bits logic [riscv::VLEN-1:0] vaddr; // virtual address out exception_t ex; // we've encountered an exception } icache_dreq_o_t; @@ -723,11 +739,12 @@ package ariane_pkg; logic [63:0] result; // sign-extended, result } amo_resp_t; - // D$ data requests + // D$ data requests typedef struct packed { logic [DCACHE_INDEX_WIDTH-1:0] address_index; logic [DCACHE_TAG_WIDTH-1:0] address_tag; riscv::xlen_t data_wdata; + logic [DCACHE_USER_WIDTH-1:0] data_wuser; logic data_req; logic data_we; logic [(riscv::XLEN/8)-1:0] data_be; @@ -740,6 +757,7 @@ package ariane_pkg; logic data_gnt; logic data_rvalid; riscv::xlen_t data_rdata; + logic [DCACHE_USER_WIDTH-1:0] data_ruser; } dcache_req_o_t; // ---------------------- @@ -826,7 +844,7 @@ package ariane_pkg; endcase return 8'b0; endfunction - + function automatic logic [3:0] be_gen_32(logic [1:0] addr, logic [1:0] size); case (size) 2'b10: begin diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index e13a76274..40e0b9c18 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -15,4 +15,9 @@ package cva6_config_pkg; localparam CVA6ConfigCvxifEn = 0; localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + endpackage diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index e13a76274..40e0b9c18 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -15,4 +15,9 @@ package cva6_config_pkg; localparam CVA6ConfigCvxifEn = 0; localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + endpackage diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index a6ba5f8aa..b5bdad940 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -15,4 +15,9 @@ package cva6_config_pkg; localparam CVA6ConfigCvxifEn = 0; localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + endpackage diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 7d2e7d17b..7af57cb15 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -15,4 +15,9 @@ package cva6_config_pkg; localparam CVA6ConfigCvxifEn = 1; localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + endpackage diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index 81c1e5d84..abaa5309a 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -77,6 +77,7 @@ package wt_cache_pkg; typedef struct packed { logic [ariane_pkg::DCACHE_TAG_WIDTH+(ariane_pkg::DCACHE_INDEX_WIDTH-riscv::XLEN_ALIGN_BYTES)-1:0] wtag; riscv::xlen_t data; + logic [ariane_pkg::DCACHE_USER_WIDTH-1:0] user; logic [(riscv::XLEN/8)-1:0] dirty; // byte is dirty logic [(riscv::XLEN/8)-1:0] valid; // byte is valid logic [(riscv::XLEN/8)-1:0] txblock; // byte is part of transaction in-flight @@ -87,7 +88,7 @@ package wt_cache_pkg; // TX status registers are indexed with the transaction ID // they basically store which bytes from which buffer entry are part // of that transaction - + typedef struct packed { logic vld; logic [(riscv::XLEN/8)-1:0] be; @@ -133,6 +134,7 @@ package wt_cache_pkg; typedef struct packed { icache_in_t rtype; // see definitions above logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data; // full cache line width + logic [ariane_pkg::ICACHE_USER_LINE_WIDTH-1:0] user; // user bits icache_inval_t inv; // invalidation vector logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) } icache_rtrn_t; @@ -151,6 +153,7 @@ package wt_cache_pkg; logic [L1D_WAY_WIDTH-1:0] way; // way to replace logic [riscv::PLEN-1:0] paddr; // physical address riscv::xlen_t data; // word width of processor (no block stores at the moment) + logic [ariane_pkg::DATA_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment) logic nc; // noncacheable logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) ariane_pkg::amo_t amo_op; // amo opcode @@ -159,6 +162,7 @@ package wt_cache_pkg; typedef struct packed { dcache_in_t rtype; // see definitions above logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // full cache line width + logic [ariane_pkg::DCACHE_USER_LINE_WIDTH-1:0] user; // user bits dcache_inval_t inv; // invalidation vector logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) } dcache_rtrn_t; @@ -311,7 +315,7 @@ package wt_cache_pkg; endcase // size return be; endfunction : to_byte_enable8 - + function automatic logic [3:0] to_byte_enable4( input logic [1:0] offset, input logic [1:0] size @@ -341,7 +345,7 @@ package wt_cache_pkg; endcase // size return out; endfunction : repData64 - + function automatic logic [31:0] repData32( input logic [31:0] data, input logic [1:0] offset, @@ -371,8 +375,8 @@ package wt_cache_pkg; endcase // be return size; endfunction : toSize64 - - + + function automatic logic [1:0] toSize32( input logic [3:0] be ); diff --git a/corev_apu/axi_mem_if b/corev_apu/axi_mem_if index 4650ca900..b49470150 160000 --- a/corev_apu/axi_mem_if +++ b/corev_apu/axi_mem_if @@ -1 +1 @@ -Subproject commit 4650ca9006d3ed7dddb3078af150467087823c19 +Subproject commit b494701501886ad71ba0c128560cc371610bcf1a diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index d926746c6..2a268bbb5 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -159,7 +159,7 @@ localparam AxiAddrWidth = 64; localparam AxiDataWidth = 64; localparam AxiIdWidthMaster = 4; localparam AxiIdWidthSlaves = AxiIdWidthMaster + $clog2(NBSlave); // 5 -localparam AxiUserWidth = 1; +localparam AxiUserWidth = ariane_pkg::AXI_USER_WIDTH; `AXI_TYPEDEF_ALL(axi_slave, logic [ AxiAddrWidth-1:0], diff --git a/corev_apu/tb/ariane_axi_soc_pkg.sv b/corev_apu/tb/ariane_axi_soc_pkg.sv index 12c3ee4ab..f143df764 100644 --- a/corev_apu/tb/ariane_axi_soc_pkg.sv +++ b/corev_apu/tb/ariane_axi_soc_pkg.sv @@ -20,7 +20,7 @@ package ariane_axi_soc; // used in axi_adapter.sv typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } ad_req_t; - localparam UserWidth = 1; + localparam UserWidth = ariane_pkg::AXI_USER_WIDTH; localparam AddrWidth = 64; localparam DataWidth = 64; localparam StrbWidth = DataWidth / 8; diff --git a/corev_apu/tb/ariane_tb.cpp b/corev_apu/tb/ariane_tb.cpp index 9d9f28b43..cc423c608 100644 --- a/corev_apu/tb/ariane_tb.cpp +++ b/corev_apu/tb/ariane_tb.cpp @@ -169,7 +169,7 @@ int main(int argc, char **argv) { case 'V': verbose = true; break; case 'p': perf = true; break; #ifdef DROMAJO - case 'D': break; + case 'D': break; #endif #if VM_TRACE case 'v': { @@ -321,6 +321,7 @@ done_processing: // Preload memory. size_t mem_size = 0xFFFFFF; memif.read(0x80000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__i_ram__DOT__Mem_DP); + // memif.read(0x84000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__gen_mem_user__DOT__i_ram_user__DOT__Mem_DP); #ifndef DROMAJO while (!dtm->done() && !jtag->done()) { diff --git a/corev_apu/tb/ariane_tb.sv b/corev_apu/tb/ariane_tb.sv index ac13b7f6c..5ec85371f 100644 --- a/corev_apu/tb/ariane_tb.sv +++ b/corev_apu/tb/ariane_tb.sv @@ -20,6 +20,7 @@ import uvm_pkg::*; `include "uvm_macros.svh" `define MAIN_MEM(P) dut.i_sram.gen_cut[0].gen_mem.i_ram.Mem_DP[(``P``)] +// `define USER_MEM(P) dut.i_sram.gen_user_cut[0].gen_user_mem.i_ram_user.Mem_DP[(``P``)] import "DPI-C" function read_elf(input string filename); import "DPI-C" function byte get_section(output longint address, output longint len); @@ -146,7 +147,7 @@ UVM_LOW) for (int j = 0; j < 8; j++) begin mem_row[j] = buffer[i*8 + j]; end - `MAIN_MEM((address[28:0] >> 3) + i) = mem_row; + `MAIN_MEM((address[23:0] >> 3) + i) = mem_row; end end end diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index c347f618b..3e9cbdc1d 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -16,7 +16,8 @@ `include "axi/assign.svh" module ariane_testharness #( - parameter int unsigned AXI_USER_WIDTH = 1, + parameter int unsigned AXI_USER_WIDTH = ariane_pkg::AXI_USER_WIDTH, + parameter int unsigned AXI_USER_EN = ariane_pkg::AXI_USER_EN, parameter int unsigned AXI_ADDRESS_WIDTH = 64, parameter int unsigned AXI_DATA_WIDTH = 64, `ifdef DROMAJO @@ -272,7 +273,9 @@ module ariane_testharness #( .we_o ( dm_slave_we ), .addr_o ( dm_slave_addr ), .be_o ( dm_slave_be ), + .user_o ( ), .data_o ( dm_slave_wdata ), + .user_i ( '0 ), .data_i ( dm_slave_rdata ) ); @@ -325,7 +328,9 @@ module ariane_testharness #( .we_o ( ), .addr_o ( rom_addr ), .be_o ( ), + .user_o ( ), .data_o ( ), + .user_i ( '0 ), .data_i ( rom_rdata ) ); @@ -384,6 +389,8 @@ module ariane_testharness #( logic [AXI_DATA_WIDTH/8-1:0] be; logic [AXI_DATA_WIDTH-1:0] wdata; logic [AXI_DATA_WIDTH-1:0] rdata; + logic [AXI_USER_WIDTH-1:0] wuser; + logic [AXI_USER_WIDTH-1:0] ruser; axi_riscv_atomics_wrap #( .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), @@ -435,12 +442,16 @@ module ariane_testharness #( .we_o ( we ), .addr_o ( addr ), .be_o ( be ), + .user_o ( wuser ), .data_o ( wdata ), + .user_i ( ruser ), .data_i ( rdata ) ); sram #( .DATA_WIDTH ( AXI_DATA_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .USER_EN ( AXI_USER_EN ), `ifdef DROMAJO .DROMAJO_RAM (1), `endif @@ -451,8 +462,10 @@ module ariane_testharness #( .req_i ( req ), .we_i ( we ), .addr_i ( addr[$clog2(NUM_WORDS)-1+$clog2(AXI_DATA_WIDTH/8):$clog2(AXI_DATA_WIDTH/8)] ), + .wuser_i ( wuser ), .wdata_i ( wdata ), .be_i ( be ), + .ruser_o ( ruser ), .rdata_o ( rdata ) );