diff --git a/CODEOWNERS b/CODEOWNERS
index 9a4976dad..77038a3c8 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -7,9 +7,18 @@ core/mmu_sv39 @sjthales
 core/cvxif_example @Gchauvon
 core/cvxif_fu.sv @Gchauvon
 
-# APU
+# HPDCache
+
+core/cache_subsystem/hpdcache @cfuguet
+core/cache_subsystem/cva6_hpdcache* @cfuguet
+core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @cfuguet
+core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv @cfuguet
+
+# OpenPiton
 
 corev_apu/openpiton @Jbalkind
+core/cache_subsystem/wt_l15_adapter.sv @Jbalkind
+core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @Jbalkind
 
 ## Documentation
 
diff --git a/core/decoder.sv b/core/decoder.sv
index de52e7f23..98fc3b1c4 100644
--- a/core/decoder.sv
+++ b/core/decoder.sv
@@ -186,6 +186,7 @@ module decoder
     ecall                                  = 1'b0;
     ebreak                                 = 1'b0;
     check_fprm                             = 1'b0;
+    tinst                                  = 32'h0;
 
     if (~ex_i.valid) begin
       case (instr.rtype.opcode)
diff --git a/core/id_stage.sv b/core/id_stage.sv
index d37554db4..121b4388b 100644
--- a/core/id_stage.sv
+++ b/core/id_stage.sv
@@ -269,6 +269,13 @@ module id_stage #(
     end else begin
       assign stall_instr_fetch[0] = stall_macro_deco;
     end
+  end else begin
+    for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
+      assign is_illegal_rvc[i] = 1'b0;
+      assign instruction_rvc[i] = fetch_entry_i[i].instruction;
+      assign is_compressed_rvc[i] = 1'b0;
+      assign stall_instr_fetch[i] = 1'b0;
+    end
   end
 
   // ---------------------------------------------------------